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1. 发明授权

US07190022B2 One transistor flash memory cell 有权
标题翻译：一个晶体管闪存单元
公开(公告)号：US07190022B2
公开(公告)日：2007-03-13
申请号：US11081886
申请日：2005-03-16
申请人： Danny Shum , Georg Tempel , Ronald Kakoschke
发明人： Danny Shum , Georg Tempel , Ronald Kakoschke
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11546
摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
摘要翻译：集成电路具有高电压区域，逻辑区域和存储器阵列，用于在包括线性，逻辑和存储器件的芯片上形成系统。存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

2. 发明授权

US07176088B2 Bitline structure and method for production thereof 有权
标题翻译：位线结构及其制造方法
公开(公告)号：US07176088B2
公开(公告)日：2007-02-13
申请号：US10513163
申请日：2004-03-18
申请人： Ronald Kakoschke , Danny Shum , Georg Tempel
发明人： Ronald Kakoschke , Danny Shum , Georg Tempel
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66833
摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.
摘要翻译：本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

3. 发明授权

US07291881B2 Bit line structure and method of fabrication 有权
公开(公告)号：US07291881B2
公开(公告)日：2007-11-06
申请号：US11592844
申请日：2006-11-02
申请人： Ronald Kakoschke , Danny Shum , Georg Tempel
发明人： Ronald Kakoschke , Danny Shum , Georg Tempel
IPC分类号： H01L29/76
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66833
摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

4. 发明申请

US20060043420A1 Bitline structure and method for production thereof 审中-公开
标题翻译：位线结构及其制造方法
公开(公告)号：US20060043420A1
公开(公告)日：2006-03-02
申请号：US10513163
申请日：2004-03-18
申请人： Ronald Kakoschke , Danny Shum , Georg Tempel
发明人： Ronald Kakoschke , Danny Shum , Georg Tempel
IPC分类号： H01L27/10
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66833
摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.
摘要翻译：本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

5. 发明授权

US06909139B2 One transistor flash memory cell 失效
标题翻译：一个晶体管闪存单元
公开(公告)号：US06909139B2
公开(公告)日：2005-06-21
申请号：US10607610
申请日：2003-06-27
申请人： Danny Shum , Georg Tempel , Ronald Kakoschke
发明人： Danny Shum , Georg Tempel , Ronald Kakoschke
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11546
摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
摘要翻译：集成电路具有高电压区域，逻辑区域和用于在包括线性，逻辑和存储器件的芯片上形成系统的存储器阵列。存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

6. 发明申请

US20070049050A1 Bit line structure and method of fabrication 有权
标题翻译：位线结构和制造方法
公开(公告)号：US20070049050A1
公开(公告)日：2007-03-01
申请号：US11592844
申请日：2006-11-02
申请人： Ronald Kakoschke , Danny Shum , Georg Tempel
发明人： Ronald Kakoschke , Danny Shum , Georg Tempel
IPC分类号： H01L21/31
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66833
摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.
摘要翻译：本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

7. 发明申请

US20050180215A1 One transistor flash memory cell 有权
公开(公告)号：US20050180215A1
公开(公告)日：2005-08-18
申请号：US11081886
申请日：2005-03-16
申请人： Danny Shum , Georg Tempel , Ronald Kakoschke
发明人： Danny Shum , Georg Tempel , Ronald Kakoschke
IPC分类号： H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11546
摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

8. 发明授权

US06800893B2 Semiconductor circuit configuration and associated fabrication method 失效
标题翻译：半导体电路配置及相关制造方法
公开(公告)号：US06800893B2
公开(公告)日：2004-10-05
申请号：US10446491
申请日：2003-05-28
申请人： Danny Shum , Georg Tempel
发明人： Danny Shum , Georg Tempel
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11568
摘要： The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of word lines and a plurality of bit lines for the row by row and column by column driving of a matrix of switching elements. In this case, a plurality of electrically conductive connection strips for connecting source and drain regions in the active region to the respective bit lines are formed between the word lines such that they directly make contact with the source and drain regions at the surface of the semiconductor substrate in the active region. In this way, a particularly compact cell area is obtained in conjunction with very simple lithographic conditions.
摘要翻译：本发明涉及一种半导体电路结构及相关的制造方法，其中半导体衬底具有用于逐行驱动开关元件矩阵的多个字线和多个位线。在这种情况下，在字线之间形成多个用于将有源区中的源区和漏区连接到各位线的导电连接条，使得它们直接与半导体的表面处的源极和漏极区接触底物在活性区域。以这种方式，结合非常简单的光刻条件获得特别紧凑的单元区域。

9. 发明授权

US06628544B2 Flash memory cell and method to achieve multiple bits per cell 有权
标题翻译：闪存单元和方法来实现每个单元的多个位
公开(公告)号：US06628544B2
公开(公告)日：2003-09-30
申请号：US10057039
申请日：2002-01-25
申请人： Danny Shum , Georg Tempel , Christoph Ludwig
发明人： Danny Shum , Georg Tempel , Christoph Ludwig
IPC分类号： G11C1604
CPC分类号： G11C11/5642 , G11C5/145 , G11C11/5628 , G11C11/5635 , G11C16/0416 , G11C16/0433 , G11C2211/565
摘要： A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.
摘要翻译：提供了一种在隧道氧化物上使用均匀电势的闪存单元编程方法。紧密的Vt分布和非常稳定的Vt在编程/擦除循环中的移位允许一个能够在每个单元上具有超过2位的多级单元。

10. 发明授权

US08389357B2 Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns 有权
标题翻译：一种具有存储阵列的存储器件的制造方法，所述存储器阵列包括以行和列排列的多个存储单元晶体管
公开(公告)号：US08389357B2
公开(公告)日：2013-03-05
申请号：US13052728
申请日：2011-03-21
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.
摘要翻译：一种在半导体衬底中制造存储器件的方法，该器件具有存储器阵列，该存储器阵列具有排列成行和列的多个存储单元晶体管。该方法包括形成多个隧穿场效应晶体管，形成第二掺杂类型的第一阱，形成围绕第一阱的第一掺杂类型的第二阱，形成连接到第一行存储单元晶体管的第一字线形成第一位线，以控制第一列存储单元晶体管的隧穿场效应晶体管的掺杂漏极区的电压，以及形成与第一位线平行的第二位线。

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