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    • 1. 发明授权
    • Method for forming conductive line of semiconductor device
    • 形成半导体器件导线的方法
    • US5629238A
    • 1997-05-13
    • US557534
    • 1995-11-14
    • Ji-hyun ChoiHong-jae ShinByung-keun HwangU-in Chung
    • Ji-hyun ChoiHong-jae ShinByung-keun HwangU-in Chung
    • H01L21/3205H01L21/316H01L21/768H01L23/522H01L21/283
    • H01L21/76831H01L21/76877
    • A method for forming a conductive line uses a fluorine doped oxide layer as an insulating layer between conductive lines. The method comprises the steps of: (a) forming a fluorine doped oxide layer on a semiconductor substrate on which a lower structure is formed; (b) etching the oxide layer of the region where a conductive line is to be formed, thereby forming a trench; (c) forming an insulating layer on the overall surface of the resultant substrate; depositing conductive material on the resultant substrate; and (e) etching back the conductive material so that the conductive material is left on the trench only, thereby forming a conductive line. In this method, the conductive line is formed of aluminum-containing material and the insulating layer is formed of silicon dioxide. In the present invention, the insulating layer is interposed between the fluorine doped oxide layer and the aluminum-containing conductive line and thus the conductive line is free from corrosion.
    • 形成导线的方法使用氟掺杂氧化物层作为导线之间的绝缘层。 该方法包括以下步骤:(a)在形成下部结构的半导体衬底上形成氟掺杂氧化物层; (b)蚀刻要形成导电线的区域的氧化物层,从而形成沟槽; (c)在所得基板的整个表面上形成绝缘层; 在所得基板上沉积导电材料; 和(e)蚀刻导电材料,使得导电材料仅留在沟槽上,从而形成导电线。 在该方法中,导电线由含铝材料形成,绝缘层由二氧化硅形成。 在本发明中,绝缘层介于氟掺杂氧化物层和含铝导电线之间,因此导电线无腐蚀。
    • 10. 发明授权
    • Trench isolation methods including plasma chemical vapor deposition and
lift off
    • 沟槽隔离方法,包括等离子体化学气相沉积和剥离
    • US6001696A
    • 1999-12-14
    • US52453
    • 1998-03-31
    • Chang-gyu KimMin-su BaekJi-hyun Choi
    • Chang-gyu KimMin-su BaekJi-hyun Choi
    • H01L21/762H01L21/76H01L21/336
    • H01L21/76224
    • Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.
    • 用于集成电路的隔离方法使用绝缘层的等离子体化学气相沉积,然后剥离以去除绝缘层的至少一部分。 特别地,在集成电路基板上形成剥离层。 在剥离层下方的剥离层和集成电路基板被蚀刻以在集成电路基板中形成沟槽。 沟槽限定在沟槽的一侧上的第一区域和比沟槽另一侧上的第一区域窄的第二区域。 然后进行等离子体化学气相沉积以在第一区域和第二区域上形成填充沟槽的绝缘层,第一区域上的绝缘层比第二区域厚。 然后蚀刻绝缘层以暴露第二区域中的剥离层。 然后将剥离层从第一区域提起。 如此形成的绝缘沟槽可以具有改进的隔离特性,并且可以通过减少的凹陷效应来平坦化。