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1. 发明授权

US5444026A Method for manufacturing semiconductor device by forming insulator-layer to suppress bubble formation 失效
标题翻译：通过形成绝缘体层以抑制气泡形成来制造半导体器件的方法
公开(公告)号：US5444026A
公开(公告)日：1995-08-22
申请号：US74761
申请日：1993-06-10
申请人： Chang-kyu Kim , Myeong-beom Lee , Ji-hyun Choi , Woo-in Joung , Young-jin Im , Won-joo Kim , Jin-gi Hong , Geung-won Kang
发明人： Chang-kyu Kim , Myeong-beom Lee , Ji-hyun Choi , Woo-in Joung , Young-jin Im , Won-joo Kim , Jin-gi Hong , Geung-won Kang
IPC分类号： H01L21/31 , H01L21/768 , H01L23/532 , H01L21/316
CPC分类号： H01L21/76838 , H01L21/76801 , H01L21/76828 , H01L21/76834 , H01L23/5329 , H01L2924/0002
摘要： The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.
摘要翻译：本发明在导电层和BPSG层之间形成中间层。在一个实施方案中，该中间层是从BPSG层吸收多余P离子以抑制气泡形成并从而防止由于BPSG层中气泡的存在而引起的短路的缓冲层。在第二实施例中，中间层是薄的氮化物层，其防止导电层和BPSG层彼此直接接触以抑制气泡的形成并且还防止由于气泡的存在而引起的短路在BPSG层。

2. 发明授权

US08624665B2 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US08624665B2
公开(公告)日：2014-01-07
申请号：US12462176
申请日：2009-07-30
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
IPC分类号： H03K3/01
CPC分类号： H01L27/10802 , G11C11/404 , G11C2207/2227 , G11C2211/4016 , H01L21/84 , H01L27/10844 , H01L29/7841
摘要： Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
摘要翻译：提供了一种操作半导体器件的方法，其中通过调整电压脉冲的定时或通过调节电压脉冲的电压电平来设置操作模式。

3. 发明授权

US08283711B2 Non-volatile memory devices having data storage layer 有权
标题翻译：具有数据存储层的非易失性存储器件
公开(公告)号：US08283711B2
公开(公告)日：2012-10-09
申请号：US12149209
申请日：2008-04-29
申请人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
发明人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
IPC分类号： H01L29/792
CPC分类号： G11C5/02 , G11C5/025 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
摘要翻译：提供了一种非易失性存储器件，其可以具有堆叠结构并且可以容易地以增加的密度集成，以及制造和使用非易失性存储器件的方法。非易失性存储器件可以包括至少一对第一电极线。至少一个第二电极线可以在所述至少一对第一电极线之间。至少一个数据存储层可以在至少一对第一电极线和至少一个第二电极线之间，并且可以局部地存储电阻变化。

4. 发明授权

US08058701B2 Antifuse structures, antifuse array structures, methods of manufacturing the same 有权
标题翻译：防污结构，反熔丝阵列结构，制造方法
公开(公告)号：US08058701B2
公开(公告)日：2011-11-15
申请号：US12216094
申请日：2008-06-30
申请人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
发明人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.
摘要翻译：提供了防泡结构，反熔丝阵列，制造方法和操作方法。反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。反熔丝阵列包括排列成阵列的多个反熔丝结构。

5. 发明授权

US08017477B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08017477B2
公开(公告)日：2011-09-13
申请号：US11704205
申请日：2007-02-09
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42352 , H01L29/66621 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.
摘要翻译：非易失性存储器件包括多个第一控制栅电极，第二控制栅电极，第一存储节点膜和第二存储节点膜。第一控制栅电极凹入半导体衬底。每个第二控制栅电极设置在两个相邻的第一控制栅电极之间。第二控制栅电极设置在第一控制栅电极上的半导体衬底上。第一存储节点膜设置在半导体衬底和第一控制栅电极之间。第二存储节点膜设置在半导体衬底和第二控制栅电极之间。一种制造非易失性存储器件的方法包括形成第一存储节点膜，形成第一控制栅电极，形成第二存储节点膜，以及形成第二控制栅电极。

6. 发明授权

US07961539B2 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US07961539B2
公开(公告)日：2011-06-14
申请号：US12591202
申请日：2009-11-12
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
IPC分类号： G11C13/00
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10844 , H01L29/7841 , H01L29/78654
摘要： Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states.
摘要翻译：提供了一种操作半导体器件的方法，其中调整栅极电压或漏极电压以便将载体添加到身体区域或从身体区域移除载体，从而实现具有多个数据状态的半导体。

7. 发明授权

US07833890B2 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US07833890B2
公开(公告)日：2010-11-16
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

8. 发明授权

US07729164B2 Non-volatile memory device, method of operating the same, and method of fabricating the same 有权
标题翻译：非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US07729164B2
公开(公告)日：2010-06-01
申请号：US12010943
申请日：2008-01-31
申请人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
发明人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.
摘要翻译：非易失性存储器件可以包括至少一个半导体层，多个控制栅电极，多个电荷存储层，至少一个第一辅助电极和/或至少一个第二辅助电极。多个控制栅电极可以凹入半导体层。多个电荷存储层可以在多个控制栅电极和半导体层之间。第一和第二辅助电极可以被布置成彼此面对。多个控制栅电极可以在第一和第二辅助电极之间并与半导体层电容耦合。

9. 发明申请

US20100027316A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100027316A1
公开(公告)日：2010-02-04
申请号：US12465125
申请日：2009-05-13
申请人： TAE-EUNG YOON , Won-joo Kim , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： TAE-EUNG YOON , Won-joo Kim , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/025
摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.
摘要翻译：具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。提供耦合在多个位线和多个可变电阻器之间的多个选择晶体管。

10. 发明申请

US20090285027A1 Non-volatile memory devices and methods of operating non-volatile memory devices 有权
标题翻译：非易失性存储器件和操作非易失性存储器件的方法
公开(公告)号：US20090285027A1
公开(公告)日：2009-11-19
申请号：US12318651
申请日：2009-01-05
申请人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.
摘要翻译：提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。从多个位线确定用于编程的选择位线和用于防止编程的未选位线。对从多个字线中选择的至少一个禁止字线施加抑制电压。至少一个禁止字线包括最靠近字符串选择线定位的字线。将编程电压施加到从多个字线中选择的选定字线。数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

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