专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5053853A Modular electronic packaging system 失效
标题翻译：模块化电子包装系统
公开(公告)号：US5053853A
公开(公告)日：1991-10-01
申请号：US520439
申请日：1990-05-08
申请人： Javad Haj-Ali-Ahmadi , Richard F. Frankeny , Karl Hermann
发明人： Javad Haj-Ali-Ahmadi , Richard F. Frankeny , Karl Hermann
IPC分类号： H01L23/473 , H01L23/40 , H01L23/42 , H01L23/433 , H01L25/00 , H01L25/065 , H05K5/00
CPC分类号： H01L23/433 , H01L23/4006 , H01L23/42 , H01L25/0655 , H05K5/0091 , H01L2023/4043 , H01L2023/4062 , H01L2023/4068 , H01L2224/16 , H01L2224/73253
摘要： An electronic circuit packaging module includes a lower substrate, an upper cooling unit, and a frame disposed between the substrate and cooling unit. The substrate carries a plurality of integrated circuit chips with lead-outs to a plurality of downwardly protruding dimpled contact points disposed about the substrate periphery. The frame includes a plurality of insulative inserts about its periphery having conductive pins each with a lower extension extending below the insert and an upper contact point recessed within the insert. The cooling unit includes a plurality of fluid bags each in contact with a respective chip on the substrate for thermal management. A plurality of such modules are stacked in vertical registry with each downwardly protruding dimple of a module extending into a respective insert recess of an adjacent module. Electrical contact is thus effected between the respective dimples on the lower surface of the upper module and respective upper contact points of the recessed pins on the upper surface of the cover module. The lower extension of the pins of each insert of a given module thus extend into contact with the upper surface of a respective dimple of an adjacent lower module. In this manner, vertical electrical interconnection is established through the pins when mated in vertical registry, establishing a plurality of conductive paths in the Z axis.

2. 发明授权

US5313097A High density memory module 失效
标题翻译：高密度内存模块
公开(公告)号：US5313097A
公开(公告)日：1994-05-17
申请号：US976770
申请日：1992-11-16
申请人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
发明人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
IPC分类号： H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18 , H05K3/32 , H01L23/02 , H02B1/00
CPC分类号： H01L25/0657 , H01L25/0652 , H05K3/325 , H01L2224/16 , H01L2224/16108 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06596
摘要： A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder connections.
摘要翻译：存储器模块由形成低电感电容器的板的形式的配电组件和柔性电路基板构成。电路基板上装有用于接触基板的存储芯片的功率，读取，写入和地址线的精确定位的接触焊盘。存储芯片固定在散热器上，并装载到芯片保持器中，芯片保持器将芯片定位成与衬底上的接触焊盘接触。将衬底接触垫电镀以形成钯的树枝晶体，并且存储器芯片在存储器芯片的接触焊盘上设置有焊球。通过将散热器夹在散热器上用于测试的压缩力，焊球与接触垫保持接触，并且组装可以容易地拆卸以代替任何有缺陷的存储器。芯片与基板的压缩连接可以依赖于或者焊球可以被回流以建立永久的焊接连接。

3. 发明授权

US5037311A High density interconnect strip 失效
标题翻译：高密度互连条
公开(公告)号：US5037311A
公开(公告)日：1991-08-06
申请号：US347695
申请日：1989-05-05
申请人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
IPC分类号： H01R43/20 , H01R12/71 , H01R13/04 , H01R13/24 , H05K1/14 , H05K3/32 , H05K3/36
CPC分类号： H01R13/2435 , H01R12/714 , H05K3/368 , H05K1/145 , H05K2201/0311 , H05K2201/0397 , H05K2201/10424 , H05K2203/167 , H05K3/325 , H05K3/365 , H05K3/366
摘要： An interconnect strip is provided for effecting electrical interconnection between pluralities of conductor pads disposed on circuit boards or the like in a high density configuration. The strip is fabricated from a polymer film carrier having laminated thereon a metal foil with preselected spring properties. After lamination, lithographic techniques from a series of electrically isolated metallic beams on the carrier. Additional chemical processing removes portions of the carrier at opposing sides of the strip to expose opposing ends of the beams which extend beyond the carrier parallel to one another in opposing directions outwards from the carrier. By urging the pads towards respective beam ends of the strip disposed between the pads until mating engagement therewith, a plurality of electrical interconnections are established through the beams. Flexural properties of the strip provide a low insertion force connection for a high density of conductors wherein the spring action of the strip assures favorable contact forces to the pads. The exposed film side of the strip may also be metalized and provided with beams or interconnected to beams on opposing side of the film by vias thereby providing a ground plane.

4. 发明授权

US5290710A Method for testing integrated circuits on a carrier substrate 失效
标题翻译：在载体基板上测试集成电路的方法
公开(公告)号：US5290710A
公开(公告)日：1994-03-01
申请号：US887995
申请日：1992-05-22
申请人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
发明人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
IPC分类号： G01R31/28 , G01R31/30 , H01L21/00 , H01L21/60 , H01L21/66 , H05K13/08 , H01L21/52 , H01L21/58
CPC分类号： G01R31/2862 , G01R31/2863 , H01L21/67098 , H01L22/00 , H01L24/75 , H01L24/81 , H05K13/08 , G01R31/287 , G01R31/2877 , H01L2224/75 , H01L2224/81801 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate.
摘要翻译：提供了一种用于测试集成电路并将成功测试的IC永久地固定到产品级载体衬底的方法和装置。使用模块化测试烘箱，其允许芯片通过非永久性地固定到载体衬底上的芯片进行电气和热学测试。如果载体基板上的所有芯片测试良好，则炉内的温度升高，从而回流焊球并将芯片永久地固定到载体基板上。

5. 发明授权

US5148003A Modular test oven 失效
标题翻译：模块化试验箱
公开(公告)号：US5148003A
公开(公告)日：1992-09-15
申请号：US619369
申请日：1990-11-28
申请人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
发明人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
IPC分类号： G01R31/28 , G01R31/30 , H01L21/00 , H01L21/60 , H01L21/66 , H05K13/08
CPC分类号： G01R31/2862 , G01R31/2863 , H01L21/67098 , H01L22/00 , H01L24/75 , H01L24/81 , H05K13/08 , G01R31/287 , G01R31/2877 , H01L2224/75 , H01L2224/81801 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate. This card can then be used in the manufacture of an electronic device without the necessity of reworking the burned-in ICs. Further, if any of the chips fail the burn-in testing, the time and overhead required for reworking is minimized since the chips are not permanently attached.
摘要翻译：提供了一种用于测试集成电路并将成功测试的IC永久地固定到产品级载体衬底的方法和装置。使用模块化测试烘箱，其允许芯片通过非永久性地固定到载体衬底上的芯片进行电气和热学测试。如果载体基板上的所有芯片测试良好，则炉内的温度升高，从而回流焊球并将芯片永久地固定到载体基板上。然后，该卡可用于电子设备的制造，而不需要对烧毁的IC进行重新加工。此外，如果任何芯片失败老化测试，则重新加工所需的时间和开销最小化，因为芯片不是永久性连接的。

6. 发明授权

US5140879A Variable array punch 失效
标题翻译：可变阵列PUNCH
公开(公告)号：US5140879A
公开(公告)日：1992-08-25
申请号：US626659
申请日：1990-12-12
申请人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Karl Hermann
发明人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Karl Hermann
IPC分类号： B21D28/24 , B26F1/04 , B28B11/12 , H05K1/03 , H05K3/00
CPC分类号： H05K3/005 , B26F1/04 , B26F2210/08 , H05K1/0306 , H05K2203/104 , Y10T83/0524 , Y10T83/0577 , Y10T83/0586 , Y10T83/8759 , Y10T83/8834
摘要： A system is provided which utilizes a plurality of sequentially controlled magnetic repulsion punches arranged in a variable array to punch a constantly moving substrate. These punches are disposed adjacent the constant velocity substrate on which holes, or vias are formed as the punches are sequentially fired. The array of punches is placed at an angle with respect to the perpendicular of the direction of movement of the substrate. Thus, a delay is present between the time when the first punch must be fired and the firing of subsequent punches, due to the angle of the array. Therefore, due to this delay between the time the first punch must energized, and the energizing of subsequent punches a single power supply is capable of providing energy to a group of punches. Further, with the system of the present invention, it is possible to punch rows of holes lying in straight rows perpendicular to the direction of movement of the substrate and have different center to center distances on the same substrate, without the necessity of rearranging the array of punches and performing an additional punching operation.

7. 发明授权

US5146674A Manufacturing process of a high density substrate design 失效
标题翻译：高密度基板设计的制造工艺
公开(公告)号：US5146674A
公开(公告)日：1992-09-15
申请号：US724245
申请日：1991-07-01
申请人： Richard F. Frankeny , Karl Hermann , Ronald L. Imken , Joseph LaTorre
发明人： Richard F. Frankeny , Karl Hermann , Ronald L. Imken , Joseph LaTorre
IPC分类号： H01L21/48 , H01L23/538 , H05K3/00 , H05K3/20 , H05K3/42 , H05K3/44 , H05K3/46
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H05K3/445 , H01L2924/0002 , H05K2201/09318 , H05K2201/09554 , H05K2201/09563 , H05K2203/0152 , H05K2203/066 , H05K2203/0733 , H05K3/0023 , H05K3/205 , H05K3/423 , H05K3/4641 , H05K3/4647 , Y10T29/49126 , Y10T29/49156
摘要： Substrate layers with individual bumps and cavities are provided which can be manufactured and tested in parallel and then joined into a multilayer substrate. The method of manufacturing these layers, as contemplated by the present invention, includes initially forming a plurality of vias in a layer of electrically conductive material. Next, a dielectric material, is placed adjacent the layer of conductive material. Holes which are coaxial with the vias are then formed in the dielectric material. Electrically conductive material is then deposited within the vias, thereby forming a conductive stud. Additional electrically conductive material is then deposited, on the side of the dielectric opposite the conductive material to form a signal layer, as well projections of electrically conductive material extending from the studs. A continuous layer of dielectric material is then placed adjacent the side of the substrate opposite the projections. A portion of this layer, adjacent the stud, is then removed, thereby exposing the stud and forming a cavity. The substrate layers can then be joined to form a multilayer substrate module.
摘要翻译：提供具有单独凸块和空腔的基板层，其可以并联制造和测试，然后连接到多层基板中。如本发明所设想的制造这些层的方法包括最初在导电材料层中形成多个通孔。接下来，将电介质材料放置在邻近导电材料层的位置。然后在电介质材料中形成与通孔同轴的孔。然后将导电材料沉积在通孔内，从而形成导电柱。然后在电介质的与导电材料相对的一侧上沉积附加的导电材料以形成信号层，以及从螺柱延伸的导电材料的突起。然后将连续的介电材料层放置成与衬底相对的与突起相对的一侧。然后去除邻近螺柱的该层的一部分，从而暴露螺柱并形成空腔。然后可以将衬底层接合以形成多层衬底模块。

8. 发明授权

US5222668A Fluid actuated connector 失效
标题翻译：流体致动连接器
公开(公告)号：US5222668A
公开(公告)日：1993-06-29
申请号：US679899
申请日：1991-04-03
申请人： Richard F. Frankeny , Karl Hermann , Ronald E. Hunt , Verlon E. Whitehead
发明人： Richard F. Frankeny , Karl Hermann , Ronald E. Hunt , Verlon E. Whitehead
IPC分类号： H01R24/00 , H01R12/85 , H01R43/00 , H05K1/14
CPC分类号： H01R12/853
摘要： A fluid actuated connector is provided with opposing circuit members that form the interior of the connector and which are substantially L-shaped with a substantially vertical portion facing a circuit card to be inserted into the connector and a substantially horizontal portion disposed onto a printed circuit board (PCB), such as a motherboard, or the like. The circuit members are disposed adjacent a frame and connector body such that a cavity is formed adjacent the circuit members and on a side opposite the electrical connection points being being contacted with the printed circuit card. The circuit membranes are formed of a single layer of dielectric material, to maintain the required resiliency, and have contacts, which may be in the form of "bumps" etched into an electrically conductive material applied to the surface of the dielectric facing the circuit card. The side of the circuit membrane in communication with the cavity, which is filled with a non-compressible fluid, receives the force that deforms the circuit membrane. In order to increase the force actually transferred to the contact bumps, rigid pads are placed on the inside of the circuit membrane such that the pressurized fluid acts directly on the rigid pads. These pads are etched into a metal layer deposited on the dielectric and placed substantially opposite the electrical contact bumps, thereby allowing transfer of the force from the fluid directly to the bumps without the intermediate layers of an expandable tube, bladder, or the like.
摘要翻译：流体致动连接器设置有形成连接器内部的相对的电路构件，其基本上为L形，其中基本垂直的部分面向要插入连接器的电路卡，并且基本上水平的部分设置在印刷电路板（PCB），例如主板等。电路构件邻近框架和连接器本体设置，使得与电路构件相邻并且与正在与印刷电路卡接触的电连接点相对的一侧形成空腔。电路膜由单层电介质材料形成，以保持所需的弹性，并且具有触点，其可以是蚀刻到施加到面向电路卡的电介质的表面的导电材料中的“凸块”形式。与填充有不可压缩流体的空腔连通的电路膜的一侧接收使电路膜变形的力。为了增加实际转移到接触凸点的力，刚性垫被放置在电路膜的内部，使得加压流体直接作用在刚性垫上。这些焊盘被蚀刻到沉积在电介质上的金属层中，并且基本上与电接触凸块相对放置，从而允许将力从流体直接传递到凸块，而不需要可膨胀管，气囊等的中间层。

9. 发明授权

US5363275A Modular component computer system 失效
标题翻译：模块化组件计算机系统
公开(公告)号：US5363275A
公开(公告)日：1994-11-08
申请号：US15989
申请日：1993-02-10
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
IPC分类号： G06F1/18 , H01L23/538 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/36 , H05K1/00
CPC分类号： H05K1/189 , H01L23/5385 , H01L23/5387 , H01L2224/16225 , H01L2924/15311 , H05K1/118 , H05K2201/041 , H05K2201/053 , H05K2201/2009 , H05K3/0058 , H05K3/361 , H05K3/4691
摘要： Discrete computational elements are provided that will be connected to a base unit, and to one another or I/O devices, in order to configure a particular computer system. The base unit provides the electrical power required to energize the computational elements. A plurality of identically configured substrates are joined in a layered relation and are electrically connected with one another. These substrates are capable of being fabricated of different lengths such that they can extend outwardly from the computational element and may be connected to other computational elements. At least one integrated circuit will be placed on one side of the joined substrates and is electrically connected to each substrate layer. In this manner the ICs will be able to communicate with chips on other computational elements. A support member is also included that stiffens the plural substrate layers and independently distributes electrical power through voltage and ground potential planes, and interconnected substrate layers, to the chips. The support member will be disposed adjacent the substrate layers on a side opposite the ICs and independently attachable to the base unit by using electrical connection pins, a pluggable lip portion, or the like.
摘要翻译：提供将连接到基本单元和彼此或I / O设备的离散计算元件，以便配置特定的计算机系统。基本单元提供激励计算元件所需的电力。多个相同配置的基板以分层关系连接并且彼此电连接。这些基板能够被制造成不同的长度，使得它们可以从计算元件向外延伸并且可以连接到其它计算元件。至少一个集成电路将被放置在接合的衬底的一侧上，并且电连接到每个衬底层。以这种方式，IC将能够与其他计算元件上的芯片通信。还包括支撑构件，其硬化多个衬底层，并且通过电压和接地电位平面以及互连的衬底层独立地分配电力到芯片。支撑构件将被布置在与IC相对的一侧上的基底层附近，并且通过使用电连接销，可插入唇部等可独立地附接到基座单元。

10. 发明授权

US5205740A Super connector for connecting flat ribbon cables 失效
标题翻译：用于连接扁平电缆的超级连接器
公开(公告)号：US5205740A
公开(公告)日：1993-04-27
申请号：US808261
申请日：1991-12-13
申请人： Richard F. Frankeny , Karl Hermann , Ronald E. Hunt , Verlon E. Whitehead
发明人： Richard F. Frankeny , Karl Hermann , Ronald E. Hunt , Verlon E. Whitehead
IPC分类号： H01R12/77 , H01R12/78
CPC分类号： H01R12/771 , H01R12/78
摘要： A connector for connecting large numbers of contact points on a flat ribbon cable to corresponding contact points on a second flat ribbon ribbon cable is described. The connector is a rigid clamping device which encompasses the cables where they join and through the use of springs and force spreaders the connections at the cable interface are completed. The connections of the cables are disposed within a chamber within the connector and rigidly clamped to prevent movement or separation of the connections.
摘要翻译：描述了用于将扁平带状电缆上的大量接触点连接到第二扁平带状电缆上的相应接触点的连接器。连接器是一种刚性夹紧装置，其包括连接在其中的电缆，并且通过使用弹簧和强力吊具，电缆接口处的连接完成。电缆的连接设置在连接器内的腔室内，并刚性夹紧，以防止连接的移动或分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式