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1. 发明申请

US20090227058A1 PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME 审中-公开
标题翻译：光电组合物及使用其制造阵列基板的方法
公开(公告)号：US20090227058A1
公开(公告)日：2009-09-10
申请号：US12347202
申请日：2008-12-31
申请人： Jeong-Min PARK , Doo-Hee JUNG , Hi-Kuk LEE , Byung-Uk KIM , Dong-Min KIM
发明人： Jeong-Min PARK , Doo-Hee JUNG , Hi-Kuk LEE , Byung-Uk KIM , Dong-Min KIM
IPC分类号： H01L21/027 , G03F7/004
CPC分类号： G03F7/0236
摘要： A photoresist composition includes; a novolac resin prepared from a phenol compound, wherein the m-cresol constitutes about 70% to about 85% by weight of the weight of the phenol compound, a diazide compound, and an organic solvent.
摘要翻译：光致抗蚀剂组合物包括：由酚化合物制备的酚醛清漆树脂，其中间甲酚构成酚化合物，重氮化合物和有机溶剂的重量的约70重量％至约85重量％。

2. 发明申请

US20140169086A1 COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：通用半导体存储器件
公开(公告)号：US20140169086A1
公开(公告)日：2014-06-19
申请号：US14105782
申请日：2013-12-13
申请人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
发明人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.
摘要翻译：存储器件包括单元阵列和公共源极线补偿电路。单元阵列包括分别连接在多个位线和一个公共源极线之间的多个正常单元单元。公共源极线补偿电路向公共源极线提供多个补偿写入电流，以补偿通过正常单元单元同时输入到共用源极线或从共模源极线输出的多个写入电流。

3. 发明申请

US20110182339A1 METHOD AND APPARATUS FOR REDUCING PEAK TO AVERAGE POWER RATIO USING PEAK WINDOWING 有权
标题翻译：使用峰值窗口降低平均功率比的峰值的方法和装置
公开(公告)号：US20110182339A1
公开(公告)日：2011-07-28
申请号：US13004271
申请日：2011-01-11
申请人： In-Tae KANG , Jung-Hwa BAE , Jung-Uk WOO , Shin-Ho KIM , Sang-Min BAE , Jong-Han LIM , Dong-Min KIM , Bo-Rham LEE
发明人： In-Tae KANG , Jung-Hwa BAE , Jung-Uk WOO , Shin-Ho KIM , Sang-Min BAE , Jong-Han LIM , Dong-Min KIM , Bo-Rham LEE
IPC分类号： H04B17/00
CPC分类号： H04L27/2624
摘要： A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances.
摘要翻译：提供了一种使用峰值窗口降低峰均功率比（PAPR）的方法和装置。在设备中，绝对值计算器计算输入信号的绝对值，减法器根据绝对值减去预定的限幅阈值电平，平滑单元根据预定的平滑方案对减法信号进行平滑处理，并输出第一个平滑信号，加法器将第一平滑信号与削波阈值电平相加，逆计算器通过将削波阈值电平乘以相加信号的倒数来输出第二平滑信号，乘法器将最终的PAPR降低信号乘以输入信号由第二平滑信号。该方法和装置在不延迟地处理具有大带宽和高数据速率的信号的同时解决过度补偿问题，从而最小化对误码率（BER）和相邻信道泄漏比（ACLR）性能的削波影响。

4. 发明申请

US20110242924A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110242924A1
公开(公告)日：2011-10-06
申请号：US13078218
申请日：2011-04-01
申请人： Dong-Min KIM , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
发明人： Dong-Min KIM , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
IPC分类号： G11C8/10
CPC分类号： G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.
摘要翻译：半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。地址控制单元访问存储单元阵列。逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

5. 发明申请

US20110223913A1 APPARATUS AND METHOD FOR CONTROLLING STATUS OF FEMTOCELL IN BROADBAND WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：用于控制无线通信系统中FEMTOCELL状态的装置和方法
公开(公告)号：US20110223913A1
公开(公告)日：2011-09-15
申请号：US13028430
申请日：2011-02-16
申请人： Young-Sung KHO , Dong-Min KIM , Tae-Hyoun KIM
发明人： Young-Sung KHO , Dong-Min KIM , Tae-Hyoun KIM
IPC分类号： H04W60/00 , H04W52/00 , H04W88/02
CPC分类号： H04W52/0206 , H04W8/02 , H04W16/30 , H04W16/32 , H04W48/16 , H04W48/17 , H04W84/045 , Y02D70/1262
摘要： An apparatus and a method for operating a terminal in a broadband wireless communication system including a macrocell and a femtocell are provided. The method includes receiving femtocell information relating to a femtocell to which the terminal is registered, determining whether the terminal enters a region where the femtocell belongs, using the femtocell information, when entering the region where the femtocell belongs, transmitting a message to wake up the femtocell, and searching for the femtocell.
摘要翻译：提供了一种用于在包括宏小区和毫微微小区的宽带无线通信系统中操作终端的装置和方法。该方法包括接收与终端所登录的毫微微小区有关的毫微微小区信息，在进入毫微微小区属于的区域时，使用毫微微小区信息，确定终端是否进入该毫微微小区所属的区域，发送消息来唤醒毫微微小区，并且搜索毫微微小区。

6. 发明申请

US20070041260A1 SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY SENSE AMPLIFIERS AND METHODS OF UTILIZING THE SAME 失效
标题翻译：具有DUMMY SENSE放大器的半导体存储器件及其使用方法
公开(公告)号：US20070041260A1
公开(公告)日：2007-02-22
申请号：US11465304
申请日：2006-08-17
申请人： Min-Ki HONG , Sang-Seok KANG , Dong-Min KIM
发明人： Min-Ki HONG , Sang-Seok KANG , Dong-Min KIM
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.
摘要翻译：提供了具有虚拟读出放大器的半导体存储器件及其利用方法。半导体存储器件的实施例可以包括至少一个虚设单元块，其包括虚设单元和存储单元。在第一方向连接虚拟单元块中的存储单元的正常位线和在第一方向上连接虚设单元的虚拟位线。还包括虚拟读出放大器，用于连接任何两个正常位线和虚拟位线。一些实施例可以改善感测虚拟单元中的存储器单元的感测容限和刷新余量，以及提高冗余效率和虚拟单元的利用。

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