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1. 发明授权

US09165637B2 Volatile memory device and a memory controller 有权
标题翻译：易失性存储器件和存储器控制器
公开(公告)号：US09165637B2
公开(公告)日：2015-10-20
申请号：US13720998
申请日：2012-12-19
申请人： Sang-Yun Kim , Jong-Pil Son , Su-A Kim , Chul-Woo Park , Hong-Sun Hwang
发明人： Sang-Yun Kim , Jong-Pil Son , Su-A Kim , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C11/408 , G11C11/4096 , G11C2211/4061
摘要： A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
摘要翻译：操作易失性存储器件的方法包括存储弱单元行的地址信息。根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

2. 发明授权

US09042152B2 Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device 有权
标题翻译：数据读取电路，具有该数据读出电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US09042152B2
公开(公告)日：2015-05-26
申请号：US13562871
申请日：2012-07-31
申请人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
发明人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C7/06 , G11C7/08 , G11C7/14 , G11C11/56
CPC分类号： G11C13/0033 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/14 , G11C11/1673 , G11C11/1693 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C2013/0042 , G11C2013/0054
摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.
摘要翻译：包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

3. 发明授权

US08934311B2 Semiconductor memory device capable of screening a weak bit and repairing the same 有权
标题翻译：半导体存储器能够筛选弱点并进行修复
公开(公告)号：US08934311B2
公开(公告)日：2015-01-13
申请号：US13604308
申请日：2012-09-05
申请人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
发明人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
IPC分类号： G11C29/44 , G11C29/50 , G11C29/00 , G11C29/04 , G11C11/41
CPC分类号： G11C29/50 , G11C11/41 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
摘要翻译：半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

4. 发明授权

US08873324B2 Method of refreshing a memory device, refresh address generator and memory device 有权
标题翻译：刷新存储器件，刷新地址发生器和存储器件的方法
公开(公告)号：US08873324B2
公开(公告)日：2014-10-28
申请号：US13240049
申请日：2011-09-22
申请人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
发明人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C11/40622 , G11C11/408
摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
摘要翻译：生成具有刷新周期的刷新地址，以刷新刷新的存储器件。当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

5. 发明授权

US08830715B2 Semiconductor memory device including vertical channel transistors 有权
标题翻译：半导体存储器件包括垂直沟道晶体管
公开(公告)号：US08830715B2
公开(公告)日：2014-09-09
申请号：US13304851
申请日：2011-11-28
申请人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
发明人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
IPC分类号： G11C5/02 , G11C11/34 , H01L27/108 , G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/062 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
摘要翻译：公开了一种半导体存储器件。半导体存储器件包括存储器阵列块，第一字线和第二字线。存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元晶体管。第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管。

6. 发明申请

US20140169086A1 COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：通用半导体存储器件
公开(公告)号：US20140169086A1
公开(公告)日：2014-06-19
申请号：US14105782
申请日：2013-12-13
申请人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
发明人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.
摘要翻译：存储器件包括单元阵列和公共源极线补偿电路。单元阵列包括分别连接在多个位线和一个公共源极线之间的多个正常单元单元。公共源极线补偿电路向公共源极线提供多个补偿写入电流，以补偿通过正常单元单元同时输入到共用源极线或从共模源极线输出的多个写入电流。

7. 发明授权

US08705297B2 Semiconductor memory devices and semiconductor memory systems 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US08705297B2
公开(公告)日：2014-04-22
申请号：US13282830
申请日：2011-10-27
申请人： Sua Kim , Chul-woo Park , Hong-sun Hwang , Hak-soo Yu
发明人： Sua Kim , Chul-woo Park , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.
摘要翻译：半导体存储器件包括至少一个存储单元块和至少一个连接单元。所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器基于第二控制信号。

8. 发明申请

US20130064008A1 DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE 有权
标题翻译：数据读取电路，包含数据读取电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US20130064008A1
公开(公告)日：2013-03-14
申请号：US13604688
申请日：2012-09-06
申请人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
发明人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
IPC分类号： G11C7/10 , G11C11/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

9. 发明申请

US20130058145A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20130058145A1
公开(公告)日：2013-03-07
申请号：US13604308
申请日：2012-09-05
申请人： Hak-soo YU , Uk-song KANG , Chul-woo PARK , Joo-sun CHOI , Hong-Sun HWANG
发明人： Hak-soo YU , Uk-song KANG , Chul-woo PARK , Joo-sun CHOI , Hong-Sun HWANG
IPC分类号： G11C29/00 , G11C15/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
摘要翻译：半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

10. 发明申请

US20130055048A1 BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM 有权
标题翻译：内存设备或系统中的页面管理
公开(公告)号：US20130055048A1
公开(公告)日：2013-02-28
申请号：US13570568
申请日：2012-08-09
申请人： HAK-SOO YU , CHUL-WOO PARK , UK-SONG KANG , JOO-SUN CHOI , HONG-SUN HWANG , JONG-PIL SON
发明人： HAK-SOO YU , CHUL-WOO PARK , UK-SONG KANG , JOO-SUN CHOI , HONG-SUN HWANG , JONG-PIL SON
IPC分类号： G11C29/04 , G06F11/16
CPC分类号： G11C29/24 , G11C29/00 , G11C29/76 , G11C29/785 , G11C2029/4402
摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.
摘要翻译：存储器件包括存储单元阵列和坏页映射。存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

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