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1. 发明授权

US5978259A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5978259A
公开(公告)日：1999-11-02
申请号：US57604
申请日：1998-04-09
申请人： Jeong-Hwan Son , Wouns Yang
发明人： Jeong-Hwan Son , Wouns Yang
IPC分类号： H01L27/10 , H01L27/02 , H01L27/108 , H01L27/115 , H01L27/12 , G11C13/00
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/1203
摘要： Provided is a semiconductor device, including: a semiconductor substrate; a first conductive type well which is formed on the semiconductor substrate; first and second field oxide layers which are formed on the well, defining the active region of the device; a node junction, where second conductive type impurity ions are heavily doped, making contact with the field oxide layer in the well; a gate electrode formed by interposing a gate oxide layer between the second field oxide layer and the node junction on the well; a switching device made from an interlevel insulating layer, for covering the gate electrode, and having a contact hole exposing the node junction on the semiconductor substrate; a storage electrode which makes contact with the node junction through the contact hole; a dielectric layer formed on the storage electrode; and a memory device made of a plate electrode which is formed on the dielectric layer.
摘要翻译：提供一种半导体器件，包括：半导体衬底; 形成在半导体基板上的第一导电型阱; 第一和第二场氧化物层，其形成在阱上，限定该器件的有源区; 其中第二导电型杂质离子被重掺杂，与阱中的场氧化物层接触; 通过在所述第二场氧化物层和所述节点之间插入栅氧化层而形成的栅电极; 由层间绝缘层制成的开关装置，用于覆盖栅电极，并具有暴露半导体衬底上的节点结的接触孔; 存储电极，其通过所述接触孔与所述节点接触; 形成在所述存储电极上的电介质层; 以及由形成在电介质层上的平板电极制成的存储器件。

2. 发明授权

US06297084B1 Method for fabricating semiconductor memory 失效
标题翻译：半导体存储器的制造方法
公开(公告)号：US06297084B1
公开(公告)日：2001-10-02
申请号：US09383635
申请日：1999-08-26
申请人： Ku Chul Joung , Wouns Yang , Kun Sik Park
发明人： Ku Chul Joung , Wouns Yang , Kun Sik Park
IPC分类号： H01L218234
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/11546
摘要： A method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer. In addition, a contact pad layer formed of a salicide layer on the cell plug layer is formed with an area larger than the plug layer for simplifying the fabrication process and securing an adequate fabrication allowance, including the steps of (1) forming metal gate electrodes on a semiconductor substrate inclusive of a cell region and a peripheral circuit region, (2) forming gate sidewalls at sides of the gate electrode layers on the cell region and forming a material layer for forming a plug on an entire surface, (3) patterning the material layer for forming a plug on the peripheral circuit region, to form a resistive layer, (4) planarizing the material layer for forming a plug on the cell region, to form a plug layer which stuffs spaces between the gate electrode layers, and (5) selectively forming contact pad layers on a top of the plug layer on the cell region and a portion of the peripheral circuit region and converting into silicide.
摘要翻译：一种制造半导体存储器的方法，其中在形成电池插头层时电阻层由与电池插塞层的材料相同的材料形成。此外，在电池插塞层上由自对准硅层形成的接触焊盘层形成有比插塞层大的区域，以简化制造工艺并确保足够的制造余量，包括以下步骤：（1）形成金属栅电极在包括单元区域和外围电路区域的半导体衬底上，（2）在单元区域的栅极电极层的侧面形成栅极侧壁，并在整个表面上形成用于形成插塞的材料层，（3）图案化用于在外围电路区域上形成插塞的材料层，以形成电阻层;（4）平坦化用于在电池区域形成插塞的材料层，以形成填充栅电极层之间的空间的插塞层;以及（5）在电池区域上的插塞层的顶部和外围电路区域的一部分上选择性地形成接触焊盘层，并转化为硅化物。

3. 发明授权

US06271113B1 Method for forming wiring in semiconductor device 有权
标题翻译：在半导体器件中形成布线的方法
公开(公告)号：US06271113B1
公开(公告)日：2001-08-07
申请号：US09472161
申请日：1999-12-27
申请人： Tak Hyun Yoon , Wouns Yang , Sang Jun Choi
发明人： Tak Hyun Yoon , Wouns Yang , Sang Jun Choi
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/32139
摘要： Method for forming a wiring in a semiconductor device having a cell array region and a peripheral region, which allows to form a micron pattern below a critical resolution of an exposure, including the steps of (1) forming a conduction layer and a sacrificial wiring layer on a substrate in succession, (2) selectively removing the sacrificial wiring layer to form a virtual wiring line having a sloped end portion, (3) forming sidewall insulating films at sides of the virtual wiring line excluding the sloped end portion, (4) removing the virtual wiring line entirely, (5) forming a mask layer on regions of the pad and peri region pads and other wirings are to be formed thereon, and (6) using the mask layer and the sidewalls in removing the conduction layer selectively, to form a micron pattern.
摘要翻译：在具有单元阵列区域和周边区域的半导体器件中形成布线的方法，其允许在暴露的临界分辨率之下形成微米图案，包括以下步骤：（1）形成导电层和牺牲布线层（2）选择性地去除牺牲布线层以形成具有倾斜端部的虚拟布线，（3）在除了倾斜端部之外的虚拟布线的侧面形成侧壁绝缘膜，（4）完全去除虚拟布线，（5）在焊盘和周边区焊盘等布线区域上形成掩模层，以及（6）使用掩模层和侧壁选择性去除导电层，以形成微米图案。

4. 发明授权

US06319768B1 Method for fabricating capacitor in dram cell 失效
标题翻译：电容器制造方法
公开(公告)号：US06319768B1
公开(公告)日：2001-11-20
申请号：US09357935
申请日：1999-07-21
申请人： Kun Sik Park , Wouns Yang
发明人： Kun Sik Park , Wouns Yang
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885
摘要： A method for fabricating a capacitor in a DRAM cell, includes the steps of: forming a plurality of wordlines each having a first cap insulating film on a semiconductor substrate; forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of each of the wordlines; forming first sidewall insulating films at the both sides of said each of the wordlines; forming first plugs for contacting either capacitor nodes or bitlines on each of the source/drain impurity regions; forming an interlayer insulating film on the semiconductor substrate and forming a contact hole to the first plugs for contacting to the bitlines therein; forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plugs, and having a second cap insulating film; forming second sidewall insulating films at both sides of each of the bitlines and selectively removing the interlayer insulating film to expose surfaces of the first plugs; forming second plugs on the first plugs for contacting the capacitor nodes; removing the second cap insulating film to a required depth; forming capacitor storage electrodes on the second plugs and the second sidewall insulating films, wherein the capacitor storage electrodes are formed by sputtering a conductive layer on an entire surface of the semiconductor substrate and subjecting the conductive layer to an anisotropic etching to remove the conductive layer on the second cap insulating films; and forming a dielectric film and a plate electrode on the semiconductor substrate.
摘要翻译：一种在DRAM单元中制造电容器的方法，包括以下步骤：在半导体衬底上形成各自具有第一帽绝缘膜的字线; 在每个字线的两侧在半导体衬底的有源区中形成源/漏杂质区; 在所述每个字线的两侧形成第一侧壁绝缘膜; 形成用于接触每个源/漏杂质区上的电容器节点或位线的第一插头; 在所述半导体基板上形成层间绝缘膜，并且在所述第一插塞中形成与所述位线接触的接触孔; 在与所述字线垂直的方向上形成多个位线，每个所述位线与所述第一插头接触，并且具有第二帽绝缘膜; 在每个位线的两侧形成第二侧壁绝缘膜，并选择性地去除层间绝缘膜以暴露第一插塞的表面; 在所述第一插头上形成用于接触所述电容器节点的第二插头; 将所述第二帽绝缘膜移除到所需的深度; 在所述第二插头和所述第二侧壁绝缘膜上形成电容器存储电极，其中所述电容器存储电极通过在所述半导体衬底的整个表面上溅射导电层并对所述导电层进行各向异性蚀刻以去除所述导电层而形成第二帽绝缘膜; 以及在所述半导体衬底上形成绝缘膜和平板电极。

5. 发明授权

US06387759B1 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06387759B1
公开(公告)日：2002-05-14
申请号：US09299577
申请日：1999-04-27
申请人： Jeong-Soo Park , Wouns Yang , Hyun-Jo Yang
发明人： Jeong-Soo Park , Wouns Yang , Hyun-Jo Yang
IPC分类号： H01L218234
CPC分类号： H01L27/11517 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11551
摘要： A method of fabricating semiconductor device is provided that includes a method of forming plugs in a semiconductor device. The plugs or contacts can connect an upper conductive layer to a lower conductive layer. The plugs are preferably formed without providing contact holes. The method of fabricating a semiconductor device can include the steps of defining an active area of a device by forming a field insulating layer on a semiconductor substrate of a first conductivity type, forming a gate oxide on an exposed surface of the active layer and forming a plurality of gates and associated cap insulating layers along a first direction perpendicular to an active area. An impurity region of a second conductivity type is formed in the exposed active area of the semiconductor substrate and a plurality of sidewall spacers are formed at sides of the gates. An electrically-conductive layer is formed for contacting the impurity region between the gates on the semiconductor substrate. The method can further include forming a plurality of plugs by patterning the electrically-conductive layer so that the plugs contact the impurity region, and an insulating interlayer is then formed where the plugs are not formed between the gates.
摘要翻译：提供一种制造半导体器件的方法，其包括在半导体器件中形成插塞的方法。插头或触点可以将上导电层连接到下导电层。塞子优选地形成而不提供接触孔。制造半导体器件的方法可以包括以下步骤：通过在第一导电类型的半导体衬底上形成场绝缘层来限定器件的有源区，在有源层的暴露表面上形成栅极氧化物，并形成多个栅极和相关联的帽绝缘层沿垂直于有效区域的第一方向。在半导体衬底的暴露的有源区域中形成第二导电类型的杂质区域，并且在栅极的侧面形成多个侧壁间隔物。形成用于接触半导体衬底上的栅极之间的杂质区的导电层。该方法还可以包括通过使导电层图案化形成多个插塞，使得插头接触杂质区域，然后形成绝缘中间层，其中插塞未形成在栅极之间。

6. 发明授权

US5849619A Method for formation of capacitors 失效
标题翻译：电容器形成方法
公开(公告)号：US5849619A
公开(公告)日：1998-12-15
申请号：US769627
申请日：1996-12-18
申请人： Won-Ju Cho , Wouns Yang
发明人： Won-Ju Cho , Wouns Yang
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming a capacitor for a DRAM includes the steps of: forming an insulating layer with a contact hole on a substrate; forming a first conductive layer on the insulating layer and in the contact hole; forming a temporary layer pattern on a portion of the first conductive layer corresponding to the contact hole; forming a second conductive layer on the first conductive layer and on the temporary layer pattern; selectively implanting oxygen ions into the first and second conductive layers except a portion of the second conductive layer corresponding to a side face of the temporary layer pattern; heat treating so as to convert the oxygen-ion-implanted first and second conductive layer portions into an oxide; removing the oxide and temporary layer pattern; forming a dielectric layer on the surface of the first and second conductive layers; and forming a third conductive layer on the dielectric layer.
摘要翻译：形成用于DRAM的电容器的方法包括以下步骤：在衬底上形成具有接触孔的绝缘层; 在绝缘层和接触孔中形成第一导电层; 在对应于接触孔的第一导电层的一部分上形成临时层图案; 在所述第一导电层和所述临时层图案上形成第二导电层; 除了对应于临时层图案的侧面的第二导电层的一部分之外，有选择地将氧离子注入到第一和第二导电层中; 热处理以将注入氧离子的第一和第二导电层部分转化为氧化物; 去除氧化物和临时层图案; 在所述第一和第二导电层的表面上形成介电层; 以及在所述电介质层上形成第三导电层。

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