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1. 发明授权

US07277977B2 DRAM for high-speed data access 失效
标题翻译： DRAM用于高速数据访问
公开(公告)号：US07277977B2
公开(公告)日：2007-10-02
申请号：US10330482
申请日：2002-12-30
申请人： Jeong-Hoon Kook , Sang-Hoon Hong , Se-Jun Kim
发明人： Jeong-Hoon Kook , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0607 , G06F2212/3042 , G11C11/4076 , G11C2207/2245
摘要： A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.
摘要翻译：具有用于数据输入/输出的通用交织方案的DRAM使用正常的存储体结构。 DRAM提供高性能而不考虑数据访问模式。为了实现高性能，DRAM包括多个正常库，至少一个与正常库具有相同数据访问方案的高速缓存组，用于选择性地以读取模式选择存储与正常存储库的数据;以及控制器，用于在连续读取命令发生到所选择的法线段时控制对高速缓存组和所选择的法线库的访问。

2. 发明授权

US06859081B2 Duty cycle correction circuit and delay locked loop having the same 失效
标题翻译：占空比校正电路和延迟锁定环具有相同的作用
公开(公告)号：US06859081B2
公开(公告)日：2005-02-22
申请号：US10638994
申请日：2003-08-11
申请人： Sang-Hoon Hong , Se-Jun Kim , Jeong-Hoon Kook
发明人： Sang-Hoon Hong , Se-Jun Kim , Jeong-Hoon Kook
IPC分类号： H03L7/08 , H03K5/156 , H03L7/081 , H03L7/089 , H03K3/017
CPC分类号： H03L7/0805 , H03K5/1565 , H03L7/0812 , H03L7/0891
摘要： A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.
摘要翻译：一种占空比校正（DCC）电路，包括用于分割普通和子输入时钟的第一和第二时钟分频器。可选的第一和第二可变延迟器件延迟分频时钟。第一和第二混频器混合可选地延迟的普通分频时钟和次普通分频时钟，或普通分频时钟和可选延迟的次普通分频时钟。包括逻辑组合装置以产生与正常和子输入时钟相同频率的时钟，具有校正的占空比。

3. 发明授权

US07174418B2 Semiconductor memory device for enhancing refresh operation in high speed data access 有权
标题翻译：用于增强高速数据访问中的刷新操作的半导体存储器件
公开(公告)号：US07174418B2
公开(公告)日：2007-02-06
申请号：US10749766
申请日：2003-12-30
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618
摘要： A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.
摘要翻译：用于刷新存储在存储器件中的数据的半导体器件包括具有N + 1个单元单元块的单元区域，每个单元单元块包括分别耦合到多个单位单元的M个字线; 具有N + 1个单位标签块的标签块，每个存储表示存储数据的行地址的至少一个物理单元块地址; 以及控制块，用于控制标签块和预定的单元块表，用于响应于物理单元块地址刷新与字线耦合的多个单元单元中的数据。

4. 发明授权

US06987409B2 Analog delay locked loop with tracking analog-digital converter 有权
标题翻译：具有跟踪模数转换器的模拟延迟锁定环
公开(公告)号：US06987409B2
公开(公告)日：2006-01-17
申请号：US10749448
申请日：2003-12-31
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： H03L7/06
CPC分类号： H03M1/48 , H03L7/0812 , H03L7/0891 , H03L7/0995
摘要： An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.
摘要翻译：模拟DLL设备包括用于建模用于缓冲外部时钟信号的延迟时间的延迟模型; 相位比较器，用于将参考时钟信号的相位与来自延迟模型的输出信号的相位进行比较; 用于泵送充电的电荷泵; 用于产生参考电压的环路滤波器; 电压控制延迟线和将参考电压转换为数字值的跟踪数模转换器; 并存储用于保持参考电压的数字值。

5. 发明授权

US06930630B1 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US06930630B1
公开(公告)日：2005-08-16
申请号：US11021963
申请日：2004-12-23
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： H03M1/06 , H03M1/48 , H03M1/68 , H03M1/12
CPC分类号： H03M1/0607 , H03M1/48 , H03M1/687
摘要： An analog-to-digital converter outputs a reliable digital value corresponding to an input analog value without regard to variation of process, temperature and driving voltage. The analog-to-digital converter includes a voltage comparator for comparing an input voltage with a comparison voltage, a binary up/down counter for up/down converting an outputted binary digital code based on the comparison result of the voltage comparator, a digital-to-analog converting unit for converting the binary digital code that is transferred from the up/down counter as the comparison voltage by using a bias voltage and an offset voltage and for outputting a feedback upper threshold voltage and a feedback lower threshold voltage, and a feedback bias unit for comparing the feedback upper threshold voltage with an upper threshold voltage having the maximum level of the input voltage to output the bias voltage and comparing the feedback lower threshold voltage with a lower threshold voltage having the minimum level of the input voltage to output the offset voltage.
摘要翻译：模数转换器输出对应于输入模拟值的可靠数字值，而不考虑过程，温度和驱动电压的变化。模数转换器包括用于将输入电压与比较电压进行比较的电压比较器，用于根据电压比较器的比较结果对输出的二进制数字代码进行上/下转换的二进制递增/递减计数器，模拟转换单元，用于通过使用偏置电压和偏移电压来转换从上/下计数器传送的二进制数字代码作为比较电压，并输出反馈上阈值电压和反馈下阈值电压，以及反馈偏置单元，用于将反馈上阈值电压与具有输入电压的最大电平的上阈值电压进行比较，以输出偏置电压，并将反馈下阈值电压与具有输入电压的最小电平的较低阈值电压进行比较以输出偏移电压。

6. 发明授权

US07078949B2 Analog delay locked loop having duty cycle correction circuit 失效
标题翻译：具有占空比校正电路的模拟延迟锁定环
公开(公告)号：US07078949B2
公开(公告)日：2006-07-18
申请号：US10750243
申请日：2003-12-31
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , H03L7/07 , H03L7/0812 , H03L7/0814
摘要： An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.
摘要翻译：模拟延迟锁定环路装置包括用于接收内部时钟信号的第一块和参考时钟信号，以产生正常的多相时钟信号对和虚拟多相时钟信号对; 以及第二块，用于接收参考时钟信号以产生具有基于正常多相时钟信号对和伪多相时钟信号对的校正占空比的延迟锁定内部时钟信号。

7. 发明授权

US06937535B2 Semiconductor memory device with reduced data access time 有权
标题翻译：具有减少数据存取时间的半导体存储器件
公开(公告)号：US06937535B2
公开(公告)日：2005-08-30
申请号：US10696144
申请日：2003-10-28
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
IPC分类号： G11C11/401 , G11C7/18 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/18 , G11C11/4087 , G11C11/4097
摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
摘要翻译：存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于从原始单元块或另一个单元块输出下一个指令。

8. 发明授权

US06930951B2 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
标题翻译：能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件
公开(公告)号：US06930951B2
公开(公告)日：2005-08-16
申请号：US10744322
申请日：2003-12-22
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/08 , G11C7/10 , G11C8/00 , G11C8/12
CPC分类号： G11C7/1018
摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.
摘要翻译：提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

9. 发明申请

US20050141324A1 Semiconductor memory device for high speed data access 有权
标题翻译：用于高速数据存取的半导体存储器件
公开(公告)号：US20050141324A1
公开(公告)日：2005-06-30
申请号：US10876380
申请日：2004-06-25
申请人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
发明人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G11C11/409 , G11C7/10 , G11C7/18 , G11C8/00 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C11/4097
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.
摘要翻译：具有用于数据传输的高速的半导体存储器件包括多个单元块，每个单元块具有用于存储数据的多个单位单元; 多个本地位线读出放大块，每个用于感测和放大存储在N个单元块中的数据; 全局位线读出放大块，用于锁存由局部位线读出放大块放大的数据; 以及数据传输块，用于将数据从本地位线读出放大块发送到全局位线读出放大块。

10. 发明授权

US08520450B2 Semiconductor memory device with optimum refresh cycle according to temperature variation 失效
标题翻译：半导体存储器件根据温度变化具有最佳的刷新周期
公开(公告)号：US08520450B2
公开(公告)日：2013-08-27
申请号：US13196779
申请日：2011-08-02
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： G11C7/06
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.
摘要翻译：公开了一种用于在半导体器件中产生刷新信号的方法和用于在半导体存储器件中执行刷新操作的方法。一种产生刷新信号的方法包括测量半导体存储器件的温度，基于测量的温度产生温度控制电压，基于温度控制电压产生N位数字信号，并产生频率为由N位数字信号决定。产生温度控制电压包括产生在测量温度降低时增加的第一电流，并且随着测量温度的升高而降低，并产生温度控制电压。

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