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1. 发明授权

US06937535B2 Semiconductor memory device with reduced data access time 有权
标题翻译：具有减少数据存取时间的半导体存储器件
公开(公告)号：US06937535B2
公开(公告)日：2005-08-30
申请号：US10696144
申请日：2003-10-28
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
IPC分类号： G11C11/401 , G11C7/18 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/18 , G11C11/4087 , G11C11/4097
摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
摘要翻译：存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于从原始单元块或另一个单元块输出下一个指令。

2. 发明授权

US06930951B2 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
标题翻译：能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件
公开(公告)号：US06930951B2
公开(公告)日：2005-08-16
申请号：US10744322
申请日：2003-12-22
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/08 , G11C7/10 , G11C8/00 , G11C8/12
CPC分类号： G11C7/1018
摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.
摘要翻译：提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

3. 发明申请

US20050141324A1 Semiconductor memory device for high speed data access 有权
标题翻译：用于高速数据存取的半导体存储器件
公开(公告)号：US20050141324A1
公开(公告)日：2005-06-30
申请号：US10876380
申请日：2004-06-25
申请人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
发明人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G11C11/409 , G11C7/10 , G11C7/18 , G11C8/00 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C11/4097
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.
摘要翻译：具有用于数据传输的高速的半导体存储器件包括多个单元块，每个单元块具有用于存储数据的多个单位单元; 多个本地位线读出放大块，每个用于感测和放大存储在N个单元块中的数据; 全局位线读出放大块，用于锁存由局部位线读出放大块放大的数据; 以及数据传输块，用于将数据从本地位线读出放大块发送到全局位线读出放大块。

4. 发明授权

US07174418B2 Semiconductor memory device for enhancing refresh operation in high speed data access 有权
标题翻译：用于增强高速数据访问中的刷新操作的半导体存储器件
公开(公告)号：US07174418B2
公开(公告)日：2007-02-06
申请号：US10749766
申请日：2003-12-30
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618
摘要： A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.
摘要翻译：用于刷新存储在存储器件中的数据的半导体器件包括具有N + 1个单元单元块的单元区域，每个单元单元块包括分别耦合到多个单位单元的M个字线; 具有N + 1个单位标签块的标签块，每个存储表示存储数据的行地址的至少一个物理单元块地址; 以及控制块，用于控制标签块和预定的单元块表，用于响应于物理单元块地址刷新与字线耦合的多个单元单元中的数据。

5. 发明申请

US20110085405A1 SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK 审中-公开
标题翻译：具有高级标签块的半导体存储器件
公开(公告)号：US20110085405A1
公开(公告)日：2011-04-14
申请号：US12969483
申请日：2010-12-15
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/00 , G11C8/10
CPC分类号： G11C8/06
摘要： A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
摘要翻译：一种半导体存储器件包括用于对输入的地址进行解码的行解码块，从而生成逻辑单元单元块地址和解码字线地址; 用于将逻辑单元单元块地址转换为物理单元单元块地址的标签块; 解码地址锁存块，用于锁存解码字线地址，从而响应于物理单元单元块将解码字线地址作为字线激活信号输出; 以及用于响应于字线激活信号输出存储在其中的数据的单元区域。

6. 发明授权

US07870362B2 Semiconductor memory device having advanced tag block 失效
标题翻译：具有高级标签块的半导体存储器件
公开(公告)号：US07870362B2
公开(公告)日：2011-01-11
申请号：US10879660
申请日：2004-06-28
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G11C8/06
摘要： A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
摘要翻译：一种半导体存储器件包括用于对输入的地址进行解码的行解码块，从而生成逻辑单元单元块地址和解码字线地址; 用于将逻辑单元单元块地址转换为物理单元单元块地址的标签块; 解码地址锁存块，用于锁存解码字线地址，从而响应于物理单元单元块将解码字线地址作为字线激活信号输出; 以及用于响应于字线激活信号输出存储在其中的数据的单元区域。

7. 再颁专利

USRE42976E1 Semiconductor memory device with reduced data access time 有权
标题翻译：具有减少数据存取时间的半导体存储器件
公开(公告)号：USRE42976E1
公开(公告)日：2011-11-29
申请号：US11897516
申请日：2007-08-29
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim , Jae-Bum Ko
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/18 , G11C11/4087 , G11C11/4097
摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.
摘要翻译：存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于从原始单元块或另一个单元块输出下一个指令。

8. 发明授权

US07363460B2 Semiconductor memory device having tag block for reducing initialization time 失效
标题翻译：具有用于减少初始化时间的标签块的半导体存储器件
公开(公告)号：US07363460B2
公开(公告)日：2008-04-22
申请号：US10749900
申请日：2003-12-30
申请人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
发明人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G11C7/1042 , G11C11/406 , G11C11/4072
摘要： A memory device includes a cell area having N+1 unit cell blocks. Each cell block includes M word lines. The N unit cell blocks are each corresponded to a logical cell block address. The one additional unit cell block is added for accessing data with high speed. A tag block receives a row address, senses the logical cell block address in the row address and outputs a physical cell block address based on the logical cell block address and the candidate information. The tag block includes:N+1 unit tag tables corresponding to the N+l unit cell blocks. Each tag block has M number of registers. The M number of registers correspond to M number of word lines of the corresponding unit cell blocks. Each register stores one logical cell block address. The tag block also includes an initialization unit that initializes the N+1 unit tag tables.
摘要翻译：存储器件包括具有N + 1个单位单元块的单元区域。每个单元格块包括M个字线。 N个单元单元块分别对应于逻辑单元块地址。添加一个附加单元单元块以高速访问数据。标签块接收行地址，感测行地址中的逻辑单元块地址，并根据逻辑单元块地址和候选信息输出物理单元块地址。标签块包括：对应于N + 1个单元块的N + 1个单元标签表。每个标签块都有M个寄存器。 M个寄存器对应于相应单元单元块的M个字线。每个寄存器存储一个逻辑单元块地址。标签块还包括初始化N + 1单位标签表的初始化单元。

9. 发明授权

US07088637B2 Semiconductor memory device for high speed data access 有权
标题翻译：用于高速数据存取的半导体存储器件
公开(公告)号：US07088637B2
公开(公告)日：2006-08-08
申请号：US10876380
申请日：2004-06-25
申请人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
发明人： Jae-Bum Ko , Jin-Hong Ahn , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G11C8/00 , G11C11/34 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.
摘要翻译：具有用于数据传输的高速的半导体存储器件包括多个单元块，每个单元块具有用于存储数据的多个单位单元; 多个本地位线读出放大块，每个用于感测和放大存储在N个单元块中的数据; 全局位线读出放大块，用于锁存由局部位线读出放大块放大的数据; 以及数据传输块，用于将数据从本地位线读出放大块发送到全局位线读出放大块。

10. 发明申请

US20050144419A1 Semiconductor memory device having advanced tag block 失效
标题翻译：具有高级标签块的半导体存储器件
公开(公告)号：US20050144419A1
公开(公告)日：2005-06-30
申请号：US10879660
申请日：2004-06-28
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C15/04 , G06F12/00 , G11C7/10 , G11C8/06
CPC分类号： G11C8/06
摘要： A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
摘要翻译：一种半导体存储器件包括用于对输入的地址进行解码的行解码块，从而生成逻辑单元单元块地址和解码字线地址; 用于将逻辑单元单元块地址转换为物理单元单元块地址的标签块; 解码地址锁存块，用于锁存解码字线地址，从而响应于物理单元单元块将解码字线地址作为字线激活信号输出; 以及用于响应于字线激活信号输出存储在其中的数据的单元区域。

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