专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07351653B2 Method for damascene process 有权
标题翻译：镶嵌工艺的方法
公开(公告)号：US07351653B2
公开(公告)日：2008-04-01
申请号：US11498888
申请日：2006-08-03
申请人： Jeong-Hoon Ahn , Kyung-Tae Lee , Yoon-Hae Kim
发明人： Jeong-Hoon Ahn , Kyung-Tae Lee , Yoon-Hae Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76822 , H01L21/7684
摘要： Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an opening penetrating the intermetal dielectric film; forming a conductive film to fill the opening on the intermetal dielectric pattern; and etching the conductive film by means of a chemical/mechanical polishing operation until exposing an upper face of the intermetal dielectric pattern and the top of the filled opening so as to form a conductive pattern. An etching process is then performed to selectively remove an upper portion of the intermetal dielectric pattern. Because the intermetal dielectric film is variable in chemical composition according to different constituent layers, the upper portion of the intermetal dielectric pattern can be selectively removed by using a chemical etching composition that demonstrates etching selectivity relative to the different layers of the intermetal dielectric film.
摘要翻译：公开了用于在半导体制造中执行镶嵌工艺的方法，包括以下步骤：在半导体衬底上形成金属间电介质膜; 图案化金属间电介质膜并形成包括至少两层不同化学组成的金属间电介质图案，其包括至少穿过金属间电介质膜的开口; 形成导电膜以填充金属间电介质图案上的开口; 并通过化学/机械抛光操作蚀刻导电膜，直到暴露金属间电介质图案的上表面和填充开口的顶部，以形成导电图案。然后执行蚀刻处理以选择性地去除金属间电介质图案的上部。由于金属间电介质膜根据不同的构成层的化学组成是可变的，所以可以通过使用相对于金属间电介质膜的不同层表现出蚀刻选择性的化学蚀刻组合物来选择性地去除金属间电介质图案的上部。

2. 发明申请

US20070037383A1 Method for damascene process 有权
标题翻译：镶嵌工艺的方法
公开(公告)号：US20070037383A1
公开(公告)日：2007-02-15
申请号：US11498888
申请日：2006-08-03
申请人： Jeong-Hoon Ahn , Kyung-Tae Lee , Yoon-Hae Kim
发明人： Jeong-Hoon Ahn , Kyung-Tae Lee , Yoon-Hae Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76822 , H01L21/7684
摘要： Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an opening penetrating the intermetal dielectric film; forming a conductive film to fill the opening on the intermetal dielectric pattern; and etching the conductive film by means of a chemical/mechanical polishing operation until exposing an upper face of the intermetal dielectric pattern and the top of the filled opening so as to form a conductive pattern. An etching process is then performed to selectively remove an upper portion of the intermetal dielectric pattern. Because the intermetal dielectric film is variable in chemical composition according to different constituent layers, the upper portion of the intermetal dielectric pattern can be selectively removed by using a chemical etching composition that demonstrates etching selectivity relative to the different layers of the intermetal dielectric film.
摘要翻译：公开了用于在半导体制造中执行镶嵌工艺的方法，包括以下步骤：在半导体衬底上形成金属间电介质膜; 图案化金属间电介质膜并形成包括至少两层不同化学组成的金属间电介质图案，其包括至少穿过金属间电介质膜的开口; 形成导电膜以填充金属间电介质图案上的开口; 并通过化学/机械抛光操作蚀刻导电膜，直到暴露金属间电介质图案的上表面和填充开口的顶部，以形成导电图案。然后执行蚀刻处理以选择性地去除金属间电介质图案的上部。由于金属间电介质膜根据不同的构成层的化学组成是可变的，所以可以通过使用相对于金属间电介质膜的不同层表现出蚀刻选择性的化学蚀刻组合物来选择性地去除金属间电介质图案的上部。

3. 发明授权

US07560332B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07560332B2
公开(公告)日：2009-07-14
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
发明人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

4. 发明授权

US07202160B2 Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
标题翻译：形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法
公开(公告)号：US07202160B2
公开(公告)日：2007-04-10
申请号：US10899934
申请日：2004-07-27
申请人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
发明人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/3122 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.
摘要翻译：在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。

5. 发明申请

US20050026422A1 Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
标题翻译：形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法
公开(公告)号：US20050026422A1
公开(公告)日：2005-02-03
申请号：US10899934
申请日：2004-07-27
申请人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
发明人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/336 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/3122 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.
摘要翻译：在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。

6. 发明授权

US07956439B2 Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same 有权
公开(公告)号：US07956439B2
公开(公告)日：2011-06-07
申请号：US11730276
申请日：2007-03-30
申请人： Cheong-Sik Yu , Kyung-Tae Lee
发明人： Cheong-Sik Yu , Kyung-Tae Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L21/76816 , H01L21/7682 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.

7. 发明授权

US08420524B2 Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same 有权
标题翻译：空隙边界结构，具有空隙边界结构的半导体器件及其形成方法
公开(公告)号：US08420524B2
公开(公告)日：2013-04-16
申请号：US13067004
申请日：2011-05-02
申请人： Cheong-Sik Yu , Kyung-Tae Lee
发明人： Cheong-Sik Yu , Kyung-Tae Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76816 , H01L21/7682 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.
摘要翻译：提供空隙边界结构，具有空隙边界结构的半导体器件及其形成方法。结构，半导体器件和方法通过在互连之间形成空隙来提供减少互连之间的寄生电容的方法。互连可以形成在半导体衬底上。每个互连的上部宽度可以比其较低的宽度宽。可以形成包含互连的成型层。可以形成覆盖模制层的空隙边界层以限定互连之间的空隙。

8. 发明授权

US07547207B2 Cooling arrangement for centering device and spline shaft 失效
标题翻译：定心装置和花键轴的冷却装置
公开(公告)号：US07547207B2
公开(公告)日：2009-06-16
申请号：US11695409
申请日：2007-04-02
申请人： Mihai Berceanu , Jeffrey Ngai , Filippo Martino , Vincent Travaglini , Kyung-Tae Lee , Gary Fong
发明人： Mihai Berceanu , Jeffrey Ngai , Filippo Martino , Vincent Travaglini , Kyung-Tae Lee , Gary Fong
IPC分类号： B29C45/74
CPC分类号： B29C45/2606 , B29C45/32 , B29C45/73
摘要： A cooling arrangement is provided for a mold centering device for multi-level stack molds having a spline shaft with a central region journaled to an intermediate mold level with involute spline pathways extending in oppositely twisting helices from the central region toward opposite ends thereof and respective spline nuts secured to adjacent mold levels threadedly engaging the spline pathways to run therealong for converting linear motion into rotational motion and vice versa thereby controlling relative opening and closing rates of the adjacent mold levels relative to the intermediate mold levels therebetween. The cooling arrangement has an internal fluid passageway extending along the spline shaft into a region of the spline shaft received in the spline nuts. A fluid inlet communicates with and supplies fluid to the fluid passageway. A fluid outlet communicates with and discharges fluid from the fluid passageway. A fluid guide is provided for causing a fluid to flow along the fluid passageway to cool the region received in the spline nuts as the fluid passes from the inlet through the outlet.
摘要翻译：提供了一种用于多级堆叠模具的模具定心装置的冷却装置，其具有花键轴，所述花键轴具有轴颈到中间模具级的中心区域，其具有从中心区域朝向其相对端延伸的相反扭转螺旋的渐开线花键路径和相应的花键螺母固定到相邻模具水平面上，螺纹地接合花键通道以沿着其运行以将线性运动转换成旋转运动，反之亦然，从而控制相邻模具水平相对于它们之间的中间模具水平的相对开启和关闭速度。冷却装置具有沿着花键轴延伸到花键螺母中的花键轴的区域中的内部流体通道。流体入口与流体通道连通并供应流体。流体出口与流体通道连通并排出流体。提供流体引导件，用于使流体沿着流体通道流动，以在流体从入口通过出口通过时冷却在花键螺母中容纳的区域。

9. 发明授权

US06911397B2 Method of forming dual damascene interconnection using low-k dielectric 有权
标题翻译：使用低k电介质形成双镶嵌互连的方法
公开(公告)号：US06911397B2
公开(公告)日：2005-06-28
申请号：US10412522
申请日：2003-04-11
申请人： Jin-Won Jun , Young-Wug Kim , Tae-Soo Park , Kyung-Tae Lee
发明人： Jin-Won Jun , Young-Wug Kim , Tae-Soo Park , Kyung-Tae Lee
IPC分类号： H01L21/28 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76807 , H01L21/02112 , H01L21/02118 , H01L21/02164 , H01L21/31116 , H01L21/312 , H01L21/3121 , H01L21/3127 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.
摘要翻译：形成双镶嵌互连的方法采用低k介电有机聚合物作为绝缘层。仅使用一个硬掩模层，使用与自对准间隔物的蚀刻速率不同的硬掩模层和蚀刻停止层来防止对绝缘层的灰化损伤。此外，可以形成小于光刻工艺的分辨率极限的通孔。结果，该过程被简化，并且不发生光致抗蚀剂尾部现象。

10. 发明授权

US09227955B2 Compound having angiogenesis inhibitory activity, method for preparing same, and pharmaceutical composition comprising same 有权
标题翻译：具有血管发生抑制活性的化合物，其制备方法和包含其的药物组合物
公开(公告)号：US09227955B2
公开(公告)日：2016-01-05
申请号：US14235439
申请日：2012-07-27
申请人： Ji Han Kim , Je Hak Kim , Joon Kwang Lee , Hahn-Sun Jung , Nam Seok Han , Yong Park , Seung-Hoon Kang , Hee Jin Jeong , Kyung-Tae Lee , Hye Eun Choi , Yong Ha Chi , Joo Han Lee , Soo Heui Paik
发明人： Ji Han Kim , Je Hak Kim , Joon Kwang Lee , Hahn-Sun Jung , Nam Seok Han , Yong Park , Seung-Hoon Kang , Hee Jin Jeong , Kyung-Tae Lee , Hye Eun Choi , Yong Ha Chi , Joo Han Lee , Soo Heui Paik
IPC分类号： C07D213/02 , C07D401/12 , C07D401/14 , C07D213/82 , C07D495/04 , C07D413/14 , C07D417/14
CPC分类号： C07D401/14 , C07D213/82 , C07D401/12 , C07D413/14 , C07D417/14 , C07D495/04
摘要： Disclosed are an anti-angiogenic compound, represented by Chemical Formula I, or a pharmaceutically acceptable salt thereof, a preparation method thereof, and a pharmaceutically acceptable composition including the same. Because the compound of Chemical Formula I potently suppresses the angiogenesis, the compound of Chemical Formula I is applicable to the prevention and treatment of diseases caused by aberrant activity of vascular endothelial growth factor, and available as an anti-angiogenic agent.
摘要翻译：公开了由化学式I表示的抗血管生成化合物或其药学上可接受的盐，其制备方法和包含其的药学上可接受的组合物。由于化学式I的化合物有效地抑制了血管生成，所以化学式I的化合物可用于预防和治疗由血管内皮生长因子的异常活性引起的疾病，并可用作抗血管生成剂。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式