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1. 发明申请

US20110189855A1 METHOD FOR CLEANING SURFACE CONTAINING Cu 审中-公开
标题翻译：清洗含Cu表面的方法
公开(公告)号：US20110189855A1
公开(公告)日：2011-08-04
申请号：US12699071
申请日：2010-02-03
申请人： Jen-Chieh Lin , Kai-Chun Yang , Chih-Yueh Li , Geng-Yu Fan , Jeng-Yu Fang , Teng-Chun Tsai , Chia-Lin Hsu
发明人： Jen-Chieh Lin , Kai-Chun Yang , Chih-Yueh Li , Geng-Yu Fan , Jeng-Yu Fang , Teng-Chun Tsai , Chia-Lin Hsu
IPC分类号： H01L21/306
CPC分类号： H01L21/306
摘要： A method for cleaning a surface is disclosed. First, a substrate including Cu and a barrier layer is provided. Second, a first chemical mechanical polishing procedure is performed on the substrate. Then, a second chemical mechanical polishing procedure is performed on the barrier layer. The second chemical mechanical polishing procedure includes performing a main chemical mechanical polishing procedure to partially remove the barrier layer and performing a chemical buffing procedure on the substrate using a chemical solution which has a pH value of about 6 to about 8 to remove residues on the substrate after the main chemical mechanical polishing procedure. Later, a water rinsing procedure is performed on the substrate. Afterwards, a post clean procedure is performed on the substrate after the second chemical mechanical polishing procedure.
摘要翻译：公开了一种清洁表面的方法。首先，提供包含Cu和阻挡层的基板。其次，在基板上进行第一化学机械抛光工序。然后，在阻挡层上进行第二化学机械抛光工序。第二化学机械抛光方法包括执行主要的化学机械抛光方法以部分去除阻挡层并使用pH值为约6至约8的化学溶液在基底上进行化学抛光过程以去除基底上的残留物经过主要的化学机械抛光程序。之后，在基板上进行水洗工序。之后，在第二化学机械抛光程序之后，在基板上执行后清洁程序。

2. 发明申请

US20120048296A1 Cleaning Method for Wafer 审中-公开
标题翻译：晶圆清洗方法
公开(公告)号：US20120048296A1
公开(公告)日：2012-03-01
申请号：US12868726
申请日：2010-08-26
申请人： Wen-Chin Lin , Kai-Chun Yang , Jen-Chieh Lin , Jeng-Yu Fang , Chia-Lin Hsu , Teng-Chun Tsai , Wei-Che Tsao
发明人： Wen-Chin Lin , Kai-Chun Yang , Jen-Chieh Lin , Jeng-Yu Fang , Chia-Lin Hsu , Teng-Chun Tsai , Wei-Che Tsao
IPC分类号： B08B7/00 , B08B3/00
CPC分类号： C11D11/0047 , C11D11/0064 , H01L21/02074
摘要： A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.
摘要翻译：提供了一种用于晶片的清洁方法。首先，进行第一清洗处理，其中第一清洗过程包括提供具有第一浓度的清洗溶液。接下来，执行第二清洁处理，其中第二清洁处理包括提供具有第二浓度的清洁溶液。第二浓度显着大于第一浓度。接下来，进行后清洗处理以提供稀释水。

3. 发明申请

US20130011938A1 METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
标题翻译：通过硅制造方法
公开(公告)号：US20130011938A1
公开(公告)日：2013-01-10
申请号：US13176790
申请日：2011-07-06
申请人： Wei-Che TSAO , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
发明人： Wei-Che TSAO , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
IPC分类号： H01L21/66 , H01L21/306 , H01L21/304
CPC分类号： H01L21/31053 , H01L21/3212 , H01L21/76898 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
摘要翻译：一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是形成。在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点干涉测量或电机电流。

4. 发明授权

US08828745B2 Method for manufacturing through-silicon via 有权
标题翻译：硅通孔制造方法
公开(公告)号：US08828745B2
公开(公告)日：2014-09-09
申请号：US13176790
申请日：2011-07-06
申请人： Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
发明人： Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
IPC分类号： H01L21/66 , H01L21/306 , H01L21/304 , H01L21/768 , H01L21/3105 , H01L21/321
CPC分类号： H01L21/31053 , H01L21/3212 , H01L21/76898 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
摘要翻译：一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是形成。在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点干涉测量或电机电流。

5. 发明授权

US08759219B2 Planarization method applied in process of manufacturing semiconductor component 有权
标题翻译：在制造半导体元件的过程中应用的平面化方法
公开(公告)号：US08759219B2
公开(公告)日：2014-06-24
申请号：US13012211
申请日：2011-01-24
申请人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
发明人： Ya-Hsueh Hsieh , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
IPC分类号： H01L21/331 , H01L21/463
CPC分类号： H01L21/7684 , H01L21/3212 , H01L29/4966 , H01L29/517
摘要： A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
摘要翻译：提供了制造半导体部件的平面化方法。介电层形成在衬底之上并在其中限定沟槽。在沟槽中依次形成阻挡层和金属层。通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

6. 发明申请

US20120187563A1 PLANARIZATION METHOD APPLIED IN PROCESS OF MANUFACTURING SEMICONDUCTOR COMPONENT 有权
标题翻译：应用于制造半导体元件的方法的平面化方法
公开(公告)号：US20120187563A1
公开(公告)日：2012-07-26
申请号：US13012211
申请日：2011-01-24
申请人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
发明人： Ya-Hsueh HSIEH , Teng-Chun Tsai , Wen-Chin Lin , Hsin-Kuo Hsu , Ren-Peng Huang , Chih-Hsien Chen , Chih-Chin Yang , Hung-Yuan Lu , Jen-Chieh Lin , Wei-Che Tsao
IPC分类号： H01L23/532 , H01L21/28
CPC分类号： H01L21/7684 , H01L21/3212 , H01L29/4966 , H01L29/517
摘要： A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
摘要翻译：提供了制造半导体部件的平面化方法。介电层形成在衬底之上并在其中限定沟槽。在沟槽中依次形成阻挡层和金属层。通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

7. 发明申请

US20120325019A1 FORCE SENSING DEVICE AND FORCE SENSING SYSTEM 审中-公开
标题翻译：力传感装置和力传感系统
公开(公告)号：US20120325019A1
公开(公告)日：2012-12-27
申请号：US13279664
申请日：2011-10-24
申请人： Yio-Wha Shau , Arvin Huang-Te Li , Gaung-Hui Gu , Bai-Kuang Hwang , Jen-Chieh Lin
发明人： Yio-Wha Shau , Arvin Huang-Te Li , Gaung-Hui Gu , Bai-Kuang Hwang , Jen-Chieh Lin
IPC分类号： G01L1/10 , G01L1/12
CPC分类号： A61B5/6807 , A61B5/1036 , A61B5/1117 , A61B5/4029 , A61B2562/0252 , A61B2562/066 , G01L1/122
摘要： A force sensing device and a force sensing system are provided. The force sensing device comprises at least one magnetic material layer and a force sensing layer which can move with respect to each other. The force sensing layer comprises two sensing elements. The first sensing element, disposed along a first axis of the magnetic material layer, generates a sensing signal varying with a first lateral force applied on the force sensing device. The first lateral force enables the first sensing element to move relatively with respect to the magnetic material layer along the first axis. The second sensing element, disposed along a second axis of the magnetic material layer, generates a sensing signal varying with a second lateral force applied on the force sensing device. The second lateral force enables the second sensing element to move relatively with respect to the magnetic material layer along the second axis.
摘要翻译：提供力传感装置和力传感系统。力感测装置包括至少一个可相对于彼此移动的磁性材料层和力感测层。力感测层包括两个感测元件。沿着磁性材料层的第一轴线设置的第一感测元件产生随施加在力感测装置上的第一横向力而变化的感测信号。第一横向力使得第一感测元件相对于磁性材料层沿着第一轴线相对移动。沿着磁性材料层的第二轴线设置的第二传感元件产生随施加在力传感器上的第二横向力而改变的传感信号。第二横向力允许第二感测元件相对于磁性材料层沿着第二轴线相对移动。

8. 发明授权

US08916066B2 Polymeric fused thiophene semiconductor formulation 有权
标题翻译：聚合稠合噻吩半导体配方
公开(公告)号：US08916066B2
公开(公告)日：2014-12-23
申请号：US13093279
申请日：2011-04-25
申请人： Mingqian He , Jianfeng Li , Jen-Chieh Lin , James Robert Matthews , Weijun Niu , Michael Lesley Sorensen
发明人： Mingqian He , Jianfeng Li , Jen-Chieh Lin , James Robert Matthews , Weijun Niu , Michael Lesley Sorensen
IPC分类号： H01B1/00 , C08G75/00 , C09D11/36 , C08K5/01 , C08L65/00
CPC分类号： C09D11/36 , C08G2261/124 , C08G2261/141 , C08G2261/3223 , C08G2261/3243 , C08G2261/92 , C08K5/01 , C08L65/00
摘要： A formulation including: an organic semiconducting material; and a carrier liquid including at least one of: a first liquid of the formulas (III) or (II): or mixtures of formulas (III) and (II); and a second liquid of a saturated or unsaturated cyclic hydrocarbylene compound of the formula (I): where the respective R1-8, x, and n are as defined herein, and optionally a tertiary liquid carrier, as defined herein. Also disclosed are semiconducting articles prepared with the formulations as defined herein.
摘要翻译：一种制剂，包括：有机半导体材料; 和包含以下至少一种的载体液体：式（III）或（II）的第一液体：或式（III）和（II）的混合物; 和式（I）的饱和或不饱和环状亚烃基化合物的第二液体：其中相应的R1-8，x和n如本文所定义，和任选地如本文所定义的叔液体载体。还公开了用本文定义的制剂制备的半导体制品。

9. 发明申请

US20070053025A1 Interpolation method for enlarging an image 失效
标题翻译：用于放大图像的插值方法
公开(公告)号：US20070053025A1
公开(公告)日：2007-03-08
申请号：US11347381
申请日：2006-02-06
申请人： Chun-Hsien Chou , Jen-Chieh Lin , Shu-Min Liau , Tsung-Hao Lee
发明人： Chun-Hsien Chou , Jen-Chieh Lin , Shu-Min Liau , Tsung-Hao Lee
IPC分类号： G06K15/02
CPC分类号： G06T3/4007
摘要： The present invention relates to an interpolation method for enlarging an image, wherein the image is composed of plural scanning lines. Firstly, it selects four adjacent continuous pixels xk−1, xk, xk+1, and xk+2 which have the pixel values f(xk−1), f(xk), f(xk+1), and f(xk+2) respectively on each of the scanning lines; next, it determines three linear equations Lk−1, Lk, and Lk+1 according to every two adjacent pixel values f(xk−1) and f(xk), f(xk) and f(xk+1), and f(xk+1) and f(xk+2), respectively; then, it selects a pixel x to be interpolated between the pixel xk and the pixel xk+1; finally, it applies the pixel x to the three linear equations Lk−1, Lk, and Lk+1 to determine three candidate pixel values which are weighted and combined to obtain pixel value f(x) of the pixel x.
摘要翻译：本发明涉及一种用于放大图像的内插方法，其中图像由多条扫描线组成。首先，它选择四个相邻的连续像素x k-1，x k，x k + 1，x k + 2 具有像素值f（x，k-1），f（x k k），f（x k + 1））和f（x＆gt; k + 2＆gt;）; 接下来，根据每两个相邻像素值f（...），它确定三个线性方程式L k-1，L k和L k + 1， f（x，k），f（x，k）和f（x k + 1） SUB>）和f（xK + 1）和f（xK + 2）; 那么它选择要在像素x SUB和像素x k + 1之间进行内插的像素x; 最后，将像素x应用于三个线性方程L k-1，L k和L k + 1，以确定三个候选像素值被加权和组合以获得像素x的像素值f（x）。

10. 发明授权

US08872286B2 Metal gate structure and fabrication method thereof 有权
标题翻译：金属栅结构及其制造方法
公开(公告)号：US08872286B2
公开(公告)日：2014-10-28
申请号：US13214260
申请日：2011-08-22
申请人： Tsun-Min Cheng , Min-Chuan Tsai , Chih-Chien Liu , Jen-Chieh Lin , Pei-Ying Li , Shao-Wei Wang , Mon-Sen Lin , Ching-Ling Lin
发明人： Tsun-Min Cheng , Min-Chuan Tsai , Chih-Chien Liu , Jen-Chieh Lin , Pei-Ying Li , Shao-Wei Wang , Mon-Sen Lin , Ching-Ling Lin
IPC分类号： H01L29/49 , H01L29/423 , H01L29/43 , H01L29/772 , H01L29/66 , H01L29/78 , H01L29/51 , H01L21/8238
CPC分类号： H01L29/4966 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L29/4232 , H01L29/435 , H01L29/51 , H01L29/66045 , H01L29/66545 , H01L29/78
摘要： A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
摘要翻译：位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。栅介质层位于衬底上。金属层位于栅极电介质层上。氮化铝钛金属层位于金属层上。

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