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1. 发明申请

US20130019117A1 Methods and Apparatus for Voltage Scaling 有权
标题翻译：电压调节的方法和装置
公开(公告)号：US20130019117A1
公开(公告)日：2013-01-17
申请号：US13183129
申请日：2011-07-14
申请人： Gerald Paul Michalak , Jeffrey Todd Bridges
发明人： Gerald Paul Michalak , Jeffrey Todd Bridges
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/26 , Y02D10/172
摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.
摘要翻译：提供了电压缩放的方法和装置。在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。时钟频率和电源电压可以在一段持续时间内保持基本上恒定。如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。确定运行极限后，将电源电压调整到运行极限内。

2. 发明授权

US09128720B2 Methods and apparatus for voltage scaling 有权
标题翻译：用于电压调节的方法和装置
公开(公告)号：US09128720B2
公开(公告)日：2015-09-08
申请号：US13183129
申请日：2011-07-14
申请人： Gerald Paul Michalak , Jeffrey Todd Bridges
发明人： Gerald Paul Michalak , Jeffrey Todd Bridges
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/3296 , G06F1/26 , Y02D10/172
摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.
摘要翻译：提供了电压缩放的方法和装置。在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。时钟频率和电源电压可以在一段持续时间内保持基本上恒定。如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。确定运行极限后，将电源电压调整到运行极限内。

3. 发明授权

US08008961B2 Adaptive clock generators, systems, and methods 有权
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：US08008961B2
公开(公告)日：2011-08-30
申请号：US12637321
申请日：2009-12-14
申请人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
发明人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

4. 发明授权

US07821350B2 Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors 有权
标题翻译：用于微处理器的锁相环的动态频率缩放的方法和装置
公开(公告)号：US07821350B2
公开(公告)日：2010-10-26
申请号：US11624995
申请日：2007-01-19
申请人： Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
发明人： Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
IPC分类号： H03L7/04
CPC分类号： H03L7/189 , H03L2207/06
摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
摘要翻译：公开了一种采用多个振荡器复合器的锁相环。锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

5. 发明授权

US07210024B2 Conditional instruction execution via emissary instruction for condition evaluation 有权
标题翻译：有条件的指令通过使用指令执行条件评估
公开(公告)号：US07210024B2
公开(公告)日：2007-04-24
申请号：US11055919
申请日：2005-02-10
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。在任一情况下，可以解决以下指令的依赖性。

6. 发明授权

US07698536B2 Method and system for providing an energy efficient register file 有权
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：US07698536B2
公开(公告)日：2010-04-13
申请号：US11201542
申请日：2005-08-10
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
IPC分类号： G06F9/00
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

7. 发明申请

US20080281996A1 Latency Insensitive FIFO Signaling Protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US20080281996A1
公开(公告)日：2008-11-13
申请号：US12179970
申请日：2008-07-25
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

8. 发明授权

US07376815B2 Methods and apparatus to insure correct predecode 有权
标题翻译：确保正确预解码的方法和装置
公开(公告)号：US07376815B2
公开(公告)日：2008-05-20
申请号：US11066957
申请日：2005-02-25
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译：公开了用于确保指令串的同步预解码的技术。指令串包含来自可变长度指令集和嵌入数据的指令。一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

9. 发明授权

US07366877B2 Speculative instruction issue in a simultaneously multithreaded processor 失效
标题翻译：同时多线程处理器中的推测性指令问题
公开(公告)号：US07366877B2
公开(公告)日：2008-04-29
申请号：US10664384
申请日：2003-09-17
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Michael Scott McIlvaine , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Michael Scott McIlvaine , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3851
摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
摘要翻译：一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

10. 发明授权

US06560677B1 Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory 失效
标题翻译：方法，缓存存储器，系统和计算机程序产品，用于在关联高速缓冲存储器中存储瞬态，正常和锁定条目
公开(公告)号：US06560677B1
公开(公告)日：2003-05-06
申请号：US09304664
申请日：1999-05-04
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F12/0864 , G06F12/121 , G06F12/126 , G06F12/128
摘要： Ways of a cache memory system are designated as being in one of three subsets: a normal subset, a transient subset, and a locked subset. The designation of the respective subsets is provided by a normal subset floor index, a transient subset floor index, and a transient subset ceiling index. The respective indexes are used to select the subset into which new entries are copied from main memory as a result of a cache miss. If the new entry is designated as being characterized by normal program behavior, it is copied into the normal subset in the cache. If the new entry is designated as being characterized by transient program behavior, it is copied into the transient subset in the cache. The relationship between the normal subset and the transient subset is programmable. For example, the normal and the transient subsets may include at least one common way of the cache memory or the transient subset may be completely included in the normal subset or completely separate therefrom.
摘要翻译：缓存存储器系统的方式被指定为三个子集之一：正常子集，瞬变子集和锁定子集。相应子集的指定由正常子集层索引，瞬时子集底层索引和瞬时子集上限索引提供。相应的索引用于选择由于高速缓存未命中而从主存储器复制新条目的子集。如果新条目被指定为通过正常程序行为表征，则将其复制到缓存中的正常子集中。如果新条目被指定为由瞬时程序行为表征，则将其复制到缓存中的瞬态子集中。正常子集与瞬态子集之间的关系是可编程的。例如，正常和瞬态子集可以包括高速缓冲存储器的至少一种常见方式，或者瞬态子集可以完全包含在正常子集中或与其完全分开。

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