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1. 发明授权

US07210024B2 Conditional instruction execution via emissary instruction for condition evaluation 有权
标题翻译：有条件的指令通过使用指令执行条件评估
公开(公告)号：US07210024B2
公开(公告)日：2007-04-24
申请号：US11055919
申请日：2005-02-10
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。在任一情况下，可以解决以下指令的依赖性。

2. 发明授权

US08661229B2 Power efficient instruction prefetch mechanism 有权
标题翻译：高效的指令预取机制
公开(公告)号：US08661229B2
公开(公告)日：2014-02-25
申请号：US12434804
申请日：2009-05-04
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

3. 发明申请

US20090210663A1 Power Efficient Instruction Prefetch Mechanism 有权
标题翻译：高效率指令预取机制
公开(公告)号：US20090210663A1
公开(公告)日：2009-08-20
申请号：US12434804
申请日：2009-05-04
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

4. 发明授权

US07624256B2 System and method wherein conditional instructions unconditionally provide output 有权
标题翻译：其中条件指令无条件地提供输出的系统和方法
公开(公告)号：US07624256B2
公开(公告)日：2009-11-24
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Andrew Sartorius , James Norris Dieffenderfer , Jeffrey Todd Bridges , Kenneth Alan Dockser , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , James Norris Dieffenderfer , Jeffrey Todd Bridges , Kenneth Alan Dockser , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F13/00
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
摘要翻译：一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便它无条件地向目标提供输出。条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。评估条件。如果满足条件，则执行操作并将操作结果输出到目标。如果条件不满足，则将先前值输出到目标。后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

5. 发明授权

US07587580B2 Power efficient instruction prefetch mechanism 有权
标题翻译：高效的指令预取机制
公开(公告)号：US07587580B2
公开(公告)日：2009-09-08
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

6. 发明授权

US07568070B2 Instruction cache having fixed number of variable length instructions 有权
标题翻译：指令缓存具有固定数量的可变长度指令
公开(公告)号：US07568070B2
公开(公告)日：2009-07-28
申请号：US11193547
申请日：2005-07-29
申请人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
IPC分类号： G06F9/34
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/382
摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.
摘要翻译：固定数量的可变长度指令存储在指令高速缓存的每一行中。可变长度指令沿预定边界排列。由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

7. 发明授权

US07415638B2 Pre-decode error handling via branch correction 有权
标题翻译：通过分支校正预解码错误处理
公开(公告)号：US07415638B2
公开(公告)日：2008-08-19
申请号：US10995858
申请日：2004-11-22
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F11/00 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。然后重新获取的指令被正确预解码，写入高速缓存并执行。

8. 发明授权

US07278012B2 Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions 有权
标题翻译：用于有效地访问第一和第二分支历史表以预测分支指令的方法和装置
公开(公告)号：US07278012B2
公开(公告)日：2007-10-02
申请号：US11144206
申请日：2005-06-02
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令，在分支目标缓存中丢失。因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

9. 发明授权

US07203826B2 Method and apparatus for managing a return stack 有权
标题翻译：用于管理返回堆栈的方法和装置
公开(公告)号：US07203826B2
公开(公告)日：2007-04-10
申请号：US11061975
申请日：2005-02-18
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4486
摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.
摘要翻译：处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回电平的数量，并且从返回堆栈中弹出该返回地址的数量。从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。补充编译器计算给定返回指令的返回值，并在编译时嵌入这些值。在另一个实施例中，返回堆栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。

10. 发明授权

US07650466B2 Method and apparatus for managing cache partitioning using a dynamic boundary 有权
标题翻译：使用动态边界管理缓存分区的方法和装置
公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

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