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1. 发明授权

US06218311B1 Post-etch treatment of a semiconductor device 有权
标题翻译：半导体器件的蚀刻后处理
公开(公告)号：US06218311B1
公开(公告)日：2001-04-17
申请号：US09334992
申请日：1999-06-17
申请人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
发明人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
IPC分类号： H01L21302
CPC分类号： H01L29/4941 , H01L21/28123 , H01L21/28176
摘要： Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.
摘要翻译：蚀刻损坏的半导体器件的蚀刻后处理包括在半导体器件的可氧化部分（18,118）上形成保护盖（48,148）。保护罩（48,148）可操作以至少抑制可氧化部分（18,118）的氧化。当可氧化部分（18,118）被覆盖时，形成氧化物结构（52,152）。氧化物结构（52,152）可操作以至少改善对半导体器件的蚀刻损伤。

2. 发明授权

US06528888B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06528888B2
公开(公告)日：2003-03-04
申请号：US09776212
申请日：2001-02-02
申请人： Chih-Chen Cho , Jeffrey A. McKee , William R. McKee , Isamu Asano , Robert Y. Tsu
发明人： Chih-Chen Cho , Jeffrey A. McKee , William R. McKee , Isamu Asano , Robert Y. Tsu
IPC分类号： H01L2348
CPC分类号： H01L27/10894 , H01L21/32051 , H01L21/32053 , H01L27/10811 , H01L27/10885
摘要： An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.
摘要翻译：集成电路。电路包括存储单元阵列，其包括形成在基板上的字线201和位线200上形成的位线200和电容器203。位线具有第一厚度和间距。电路还包括阵列外围的电路，包括形成在衬底中的晶体管和晶体管上的导体202。导体具有第二厚度和间距。电路的特征还在于，位线和导体形成在公共导电层中。在另外的实施例中，第一厚度和间距小于第二厚度和间距。

3. 发明授权

US07323727B2 System with meshed power and signal buses on cell array 有权
标题翻译：具有网格功率和信号总线的单元阵列系统
公开(公告)号：US07323727B2
公开(公告)日：2008-01-29
申请号：US11683930
申请日：2007-03-08
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L27/10
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
摘要翻译：一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。网格系统的功率和信号总线跨阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。一旦连接，总线延伸到适当的感应放大器驱动器。通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

4. 发明授权

US06831317B2 System with meshed power and signal buses on cell array 有权
标题翻译：具有网格功率和信号总线的单元阵列系统
公开(公告)号：US06831317B2
公开(公告)日：2004-12-14
申请号：US10315307
申请日：2002-12-10
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L31119
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
摘要翻译：一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。网格系统的功率和信号总线跨越阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。一旦连接，总线延伸到适当的感应放大器驱动器。通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

5. 发明授权

US06294420B1 Integrated circuit capacitor 失效
标题翻译：集成电路电容
公开(公告)号：US06294420B1
公开(公告)日：2001-09-25
申请号：US09014724
申请日：1998-01-28
申请人： Robert Tsu , Isamu Asano , Shinpei Iijima , William R. McKee
发明人： Robert Tsu , Isamu Asano , Shinpei Iijima , William R. McKee
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28518 , H01L21/76897 , H01L28/55 , H01L28/90
摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.
摘要翻译：本发明公开了一种新颖的集成电路电容器及其形成方法。电容器形成从邻近绝缘区域26的基极18开始。该基极18可以包括多晶硅或金属。诸如硅化金属的第一材料的层28形成在基极电极18上以及相邻的绝缘区域上。然后可以通过使第一材料28与基底电极18反应并从绝缘区域26去除第一材料28的未反应部分来形成自对准电容器电极12.然后通过在电容器电极12上形成介电层16来完成电容器自对准电容器电极12和在电介质层16上的第二电容器电极14。

6. 发明授权

US06288925B1 System with meshed power and signal buses on cell array 有权
标题翻译：具有网格功率和信号总线的单元阵列系统
公开(公告)号：US06288925B1
公开(公告)日：2001-09-11
申请号：US09496079
申请日：2000-02-01
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： G11C506
CPC分类号： G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
摘要翻译：一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。网格系统的功率和信号总线跨越阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。一旦连接，总线延伸到适当的感应放大器驱动器。通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

7. 发明授权

US5216265A Integrated circuit memory devices with high angle implant around top of trench to reduce gated diode leakage 失效
标题翻译：集成电路存储器件，在沟槽顶部具有高角度注入以减少栅极二极管泄漏
公开(公告)号：US5216265A
公开(公告)日：1993-06-01
申请号：US809812
申请日：1991-12-18
申请人： Dirk N. Anderson , William R. McKee , Cishi Chung
发明人： Dirk N. Anderson , William R. McKee , Cishi Chung
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/334
CPC分类号： H01L29/66181 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/26586 , H01L21/31662 , H01L21/32
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。第二倾斜的角度优选地比第一倾斜的角度更大，更高。这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。

8. 再颁专利

USRE31473E System for fabrication of semiconductor bodies 失效
标题翻译：半导体器件制造系统
公开(公告)号：USRE31473E
公开(公告)日：1983-12-27
申请号：US354015
申请日：1982-03-02
申请人： Jack S. Kilby , William R. McKee , Wilbur A. Porter
发明人： Jack S. Kilby , William R. McKee , Wilbur A. Porter
IPC分类号： B22F9/08 , C30B11/00
CPC分类号： C30B29/06 , B22F9/08 , C30B11/00 , C30B29/60
摘要： A system and method is provided for forming semiconductor tear-drop shaped bodies having minimal grain boundaries. Semiconductor material is melted in a capillary tube at the top of a tower, and forced under gas pressure through a nozzle. Separate semiconductor bodies are formed. They are passed through a free fall path over which a predetermined temperature gradient controls solidification of the bodies. The resultant bodies are tear-drop semiconductor bodies of near uniform size with minimal grain boundaries.

9. 发明授权

US07402514B2 Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer 有权
标题翻译：使用用于低介电常数层间和层间（或金属间和内部）介电层的电介质衬垫的线间可靠性增强
公开(公告)号：US07402514B2
公开(公告)日：2008-07-22
申请号：US10350451
申请日：2003-01-24
申请人： Robert Tsu , Joe W. McPherson , William R. McKee , Thomas Bonifield
发明人： Robert Tsu , Joe W. McPherson , William R. McKee , Thomas Bonifield
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.
摘要翻译：本发明的一个实施例是一种在第一导体和第二导体之间提供连接的方法，其中第一导体位于第二导体下方并由第一绝缘层分开，该方法包括以下步骤：在第一绝缘层（图1-4的层124或128），开口具有顶部，底部和侧壁，并且位于第一导体和第二导体之间; 仅在开口的侧壁上形成第二绝缘层（图3和4的层134,138和142），从而在第一绝缘层中留下较小的开口; 在较小的开口中形成导电材料（图3和图4的材料140）并且其中所述第一绝缘层由低k材料构成，并且所述第二绝缘层由具有小于所述第一绝缘层的漏电特性的漏电特性的绝缘体构成。

10. 发明授权

US06815742B2 System with meshed power and signal buses on cell array 失效
公开(公告)号：US06815742B2
公开(公告)日：2004-11-09
申请号：US10728682
申请日：2003-12-05
申请人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L31112
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

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