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1. 发明申请

US20050285652A1 Interpolator linearity testing system 失效
标题翻译：内插线性度测试系统
公开(公告)号：US20050285652A1
公开(公告)日：2005-12-29
申请号：US10879676
申请日：2004-06-29
申请人： Adarsh Panikkar , Kersi Vakil , Abhimanyu Kolla , Arnaud Forestier
发明人： Adarsh Panikkar , Kersi Vakil , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： H03K5/00 , H03K5/13 , H03K5/135 , H03K5/22 , H03L7/081 , H03L7/091
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K2005/00156 , H03L7/091
摘要： According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.
摘要翻译：根据一些实施例，接收具有第一频率的内插时钟信号，并且基于参考时钟信号周期性地采样内插时钟信号，以产生周期性采样的值，该参考时钟信号基本上具有第一频率。内插时钟信号的相位可以被设置为周期采样值解析为多于一个值的相位程度，并且内插时钟信号的相位可以被增量地改变，直到周期性采样值解析为一个值。内插时钟信号的非线性可以基于增量变化的数量来确定。

2. 发明申请

US20050280452A1 Interpolator testing system 失效
标题翻译：内插测试系统
公开(公告)号：US20050280452A1
公开(公告)日：2005-12-22
申请号：US10869573
申请日：2004-06-16
申请人： Kersi Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
发明人： Kersi Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： G01R31/317 , G11C29/02 , H03K5/00 , H03K5/13 , H03L7/00
CPC分类号： G01R31/31727 , G11C29/02 , G11C29/023 , H03K5/13 , H03K2005/00052
摘要： According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.
摘要翻译：根据一些实施例，一种设备包括内插器，用于接收具有第一时钟相位的至少第一时钟信号并且接收具有第二时钟相位的第二时钟信号。内插器可以包括与第一时钟信号相关联的第一多个内插器支路，与第二时钟信号相关联的第二多个内插器支路，以及输出节点，用于提供具有基于第一时钟的输出时钟相位的输出时钟信号信号，第二时钟信号，以及被激活的多个第一和第二多个内插器支路的数量。该装置还可以包括内插器控制，以仅激活第一多个和第二多个内插器腿中的一个。

3. 发明授权

US07043392B2 Interpolator testing system 失效
标题翻译：内插测试系统
公开(公告)号：US07043392B2
公开(公告)日：2006-05-09
申请号：US10869573
申请日：2004-06-16
申请人： Kersi H. Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
发明人： Kersi H. Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： G06F1/12
CPC分类号： G01R31/31727 , G11C29/02 , G11C29/023 , H03K5/13 , H03K2005/00052
摘要： According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.
摘要翻译：根据一些实施例，一种设备包括内插器，用于接收具有第一时钟相位的至少第一时钟信号并且接收具有第二时钟相位的第二时钟信号。内插器可以包括与第一时钟信号相关联的第一多个内插器支路，与第二时钟信号相关联的第二多个内插器支路，以及输出节点，用于提供具有基于第一时钟的输出时钟相位的输出时钟信号信号，第二时钟信号，以及被激活的多个第一和第二多个内插器支路的数量。该装置还可以包括内插器控制，以仅激活第一多个和第二多个内插器腿中的一个。

4. 发明授权

US07009431B2 Interpolator linearity testing system 失效
标题翻译：内插线性度测试系统
公开(公告)号：US07009431B2
公开(公告)日：2006-03-07
申请号：US10879676
申请日：2004-06-29
申请人： Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla , Arnaud Forestier
发明人： Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K2005/00156 , H03L7/091
摘要： According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.
摘要翻译：根据一些实施例，接收具有第一频率的内插时钟信号，并且基于参考时钟信号周期性地采样内插时钟信号，以产生周期性采样的值，该参考时钟信号基本上具有第一频率。内插时钟信号的相位可以被设置为周期采样值解析为多于一个值的相位程度，并且内插时钟信号的相位可以被增量地改变，直到周期性采样值解析为一个值。内插时钟信号的非线性可以基于增量变化的数量来确定。

5. 发明授权

US07656983B2 Dual clock domain deskew circuit 有权
标题翻译：双时钟域偏移电路
公开(公告)号：US07656983B2
公开(公告)日：2010-02-02
申请号：US11541427
申请日：2006-09-29
申请人： Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
发明人： Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L25/14
摘要： In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
摘要翻译：通常，在一个方面，本公开描述了一种包括第一台式偏移单元和第二台式偏移单元的设备。第一台逆变器单元在第一时钟域工作，并为信号提供精确的时序调整。第二个偏移校正单元在比第一时钟域慢的第二时钟域处工作，并且为信号提供粗略的时序调整。

6. 发明申请

US20060050822A1 Training pattern for a biased clock recovery tracking loop 有权
标题翻译：有针对性的时钟恢复跟踪循环的训练模式
公开(公告)号：US20060050822A1
公开(公告)日：2006-03-09
申请号：US10935903
申请日：2004-09-07
申请人： Adarsh Panikkar , Kersi Vakil , Pete Vogt
发明人： Adarsh Panikkar , Kersi Vakil , Pete Vogt
IPC分类号： H04L7/00
CPC分类号： H04L7/041 , H04L7/044 , H04L7/046
摘要： Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.
摘要翻译：本发明的一些实施例提供可包括编码信息的偏置跟踪环路。实施例可以包括以允许时钟恢复，嵌入式信息传输和/或头部对准的非干扰方式使用的训练模式。因此，实施例可以包括包括数据的跟踪循环训练模式。

7. 发明申请

US20050286565A1 Various methods and apparatuses for lane to lane deskewing 有权
标题翻译：用于车道到车道偏移校正的各种方法和装置
公开(公告)号：US20050286565A1
公开(公告)日：2005-12-29
申请号：US10881097
申请日：2004-06-29
申请人： Kersi Vakil , Adarsh Panikkar
发明人： Kersi Vakil , Adarsh Panikkar
IPC分类号： G06F1/10 , H04J3/06
CPC分类号： G06F1/10
摘要： Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.
摘要翻译：描述了确定通信通道之间的偏斜延迟时间的各种方法，装置和系统。在通信链路中建立包括两个或更多个通信线路的数据传输路径。通过使用输入输出电路的时钟周期作为参考时间，在通信链路的通信通道之间确定相位差延迟时间。

8. 发明授权

US07672335B2 Non-integer word size translation through rotation of different buffer alignment channels 失效
标题翻译：通过旋转不同缓冲器对齐通道的非整数字大小转换
公开(公告)号：US07672335B2
公开(公告)日：2010-03-02
申请号：US10733100
申请日：2003-12-10
申请人： Adarsh Panikkar , Wayne C. Ashby , Abhimanyu Kolla
发明人： Adarsh Panikkar , Wayne C. Ashby , Abhimanyu Kolla
IPC分类号： H04J3/00
CPC分类号： H04J3/0608
摘要： A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.
摘要翻译：描述了一种涉及一次将X位加载到移位寄存器中的方法，并且将移位寄存器中较旧的加载的X位组移位到每个新的加载的X位组。已从串行数据流接收每组X位。该方法还涉及通过从移位寄存器中旋转选择第一组Y连续位和从移位寄存器的第二组Y连续位中选出来自串行数据流的对准数据，识别。 Y大于X.

9. 发明授权

US07500131B2 Training pattern based de-skew mechanism and frame alignment 有权
标题翻译：基于训练模式的偏斜机制和框架对齐
公开(公告)号：US07500131B2
公开(公告)日：2009-03-03
申请号：US10935902
申请日：2004-09-07
申请人： Adarsh Panikkar , S. Reji Kumar , Daniel Klowden , Abhimanyu Kolla
发明人： Adarsh Panikkar , S. Reji Kumar , Daniel Klowden , Abhimanyu Kolla
IPC分类号： G06F1/24
CPC分类号： G06F1/12 , H04J3/0605
摘要： Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.
摘要翻译：本发明的一些实施例提供了可用于在训练序列偏斜校正中实施的去歪斜过程或协议中的训练序列。实施例还可以包括允许头部或框架对准的训练模式。

10. 发明申请

US20080080654A1 Dual clock domain deskew circuit 有权
标题翻译：双时钟域偏移电路
公开(公告)号：US20080080654A1
公开(公告)日：2008-04-03
申请号：US11541427
申请日：2006-09-29
申请人： Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
发明人： Daniel S. Klowden , S. Reji Kumar , Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla
IPC分类号： H04L7/00
CPC分类号： H04L25/14
摘要： In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
摘要翻译：通常，在一个方面，本公开描述了一种包括第一台式偏移单元和第二台式偏移单元的设备。第一台逆变器单元在第一时钟域工作，并为信号提供精确的时序调整。第二个偏移校正单元在比第一时钟域慢的第二时钟域处工作，并且为信号提供粗略的时序调整。

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