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    • 3. 发明授权
    • Interpolator testing system
    • 内插测试系统
    • US07043392B2
    • 2006-05-09
    • US10869573
    • 2004-06-16
    • Kersi H. VakilAdarsh PanikkarAbhimanyu KollaArnaud Forestier
    • Kersi H. VakilAdarsh PanikkarAbhimanyu KollaArnaud Forestier
    • G06F1/12
    • G01R31/31727G11C29/02G11C29/023H03K5/13H03K2005/00052
    • According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.
    • 根据一些实施例,一种设备包括内插器,用于接收具有第一时钟相位的至少第一时钟信号并且接收具有第二时钟相位的第二时钟信号。 内插器可以包括与第一时钟信号相关联的第一多个内插器支路,与第二时钟信号相关联的第二多个内插器支路,以及输出节点,用于提供具有基于第一时钟的输出时钟相位的输出时钟信号 信号,第二时钟信号,以及被激活的多个第一和第二多个内插器支路的数量。 该装置还可以包括内插器控制,以仅激活第一多个和第二多个内插器腿中的一个。