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1. 发明授权

US5923664A Method and apparatus providing a multiport physical interface to high speed packet networks 失效
标题翻译：向高速分组网络提供多端口物理接口的方法和装置
公开(公告)号：US5923664A
公开(公告)日：1999-07-13
申请号：US824941
申请日：1997-03-27
申请人： Jean-Paul Aldebert , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
发明人： Jean-Paul Aldebert , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/16 , H04J3/22 , H04J3/24
CPC分类号： H04Q11/0478 , H04L2012/5615
摘要： The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports. Finally, the solution of the present invention takes into account two characteristics of the physical interface which are the different rates between network link media speed and bus access rate and the technology of the high density static imbedded RAMs used for hardware integration. The Flip/Flop pointer RAMs of Flip/Flop data RAMs are duplicated and some interface RAMs are created to transfer control data between the islands and the generalized processing logical blocks.
摘要翻译：本发明公开了一种在连接到诸如异步传输模式（ATM）网络的分组网络的网络元件中实现物理接口的方法和装置。通过本发明的解决方案，物理接口功能可以集成在多个网络端口的一个芯片上。在媒体速度的端口比特流之间提供物理接口，并且传输到/经由网络设备控制的总线上的字数据流。本发明的解决方案包括通过多于一个端口的岛分组逻辑和存储元件。此外，用于统计计数操作的逻辑和存储元件可以被分组用于对所有端口进行泛化。最后，本发明的解决方案考虑了物理接口的两个特征，它们是网络链路媒体速度和总线访问速率之间的不同速率以及用于硬件集成的高密度静态嵌入RAM的技术。翻转/翻转数据RAM的翻转/翻转指针RAM被复制，并且创建一些接口RAM以在岛和广义处理逻辑块之间传送控制数据。

2. 发明授权

US5794033A Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device 失效
标题翻译：在网络设备中进行远程加载的硬件逻辑的现场和在线重新编程的方法和系统
公开(公告)号：US5794033A
公开(公告)日：1998-08-11
申请号：US547635
申请日：1995-10-24
申请人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
发明人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
IPC分类号： G06F13/38 , H03K19/177
CPC分类号： G06F13/4256
摘要： The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.
摘要翻译：本发明公开了一种用于使用远程加载的配置数据文件进行现场可编程门阵列的在线和现场更新的方法和装置。由于其非易失性存储器及其高密度使用的闪存EEPROM存储多个配置数据文件。存储器分为多个部分，存储器的每个部分用于存储一个配置数据文件。存储器的一部分还包含标识当前加载的配置数据文件的标志。闪存EPROM的位在任何写入操作之前被设置为相同的二进制值，包括更新包含该标志的配置数据文件。对所述二进制值的位的设置总是标识有效的其他配置数据文件，以便在接收到导致初始化的意外事件的情况下确保正确地重新加载FPGA。

3. 发明申请

US20070067478A1 Data aligner in reconfigurable computing environment technical field 失效
标题翻译：数据对准器在可重构计算环境技术领域
公开(公告)号：US20070067478A1
公开(公告)日：2007-03-22
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
发明人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

4. 发明授权

US06789234B2 Method and system for a timing based logic entry 失效
标题翻译：基于定时的逻辑输入的方法和系统
公开(公告)号：US06789234B2
公开(公告)日：2004-09-07
申请号：US10328355
申请日：2002-12-23
申请人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
发明人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer. The method includes first in creating timing diagrams identifying the elements of the circuit and their time based interconnections. The method further comprises a translation of the timing based diagram editor files into HDL statement. The preferred embodiment is described, it comprises the use of an ASCII editor and a translation program to VHDL statements. A system is also described implementing the steps of the method in a computer. In order to avoid having different tools to translate timing based diagram editor files into HDL statements, a first step translating graphical editor output file into a PostScript file is performed by executing the “print to file” command of the printing driver of the computer. The PostScript file is then translated into a bitmap file using a RIP. The translation is then performed from the bitmap file into the HDL statements. This translation is “universal” as it can be used for any type of initial graphical file containing the timing diagram.
摘要翻译：一种用于在计算机上创建使用在计算机上操作的图形编辑器的基于时序的集成电路表示的方法和系统。该方法首先在创建识别电路的元件及其基于时间的互连的时序图。该方法还包括将基于时序的编辑器文件转换为HDL语句。描述了优选实施例，它包括使用ASCII编辑器和对VHDL语句的翻译程序。还描述了在计算机中实现该方法的步骤的系统。为了避免使用不同的工具将基于时序的图编辑器文件转换为HDL语句，将图形编辑器输出文件转换为PostScript文件的第一步是通过执行计算机打印驱动程序的“打印到文件”命令执行的。然后使用RIP将PostScript文件转换为位图文件。然后，转换从位图文件执行到HDL语句。这个翻译是“通用的”，因为它可以用于包含时序图的任何类型的初始图形文件。

5. 发明授权

US6144637A Data communications 失效
标题翻译：数据通信
公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

6. 发明授权

US5724348A Efficient hardware/software interface for a data switch 失效
标题翻译：高效的数据交换硬件/软件界面
公开(公告)号：US5724348A
公开(公告)日：1998-03-03
申请号：US858156
申请日：1997-05-05
申请人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/30 , H04L49/104 , H04L49/254 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/5652 , H04L49/3009
摘要： A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.
摘要翻译：使用多端口数据交换元件描述数据交换机，一个或多个输入/输出适配器，用于从交换机外部接收用户数据单元，以及将通过交换单元切换的小区发送到交换机外部的网络，以及控制元件包括一个控制处理器。为了降低数据交换的复杂性，单个控制处理器用于控制处理器所在的控制元件和输入/输出适配器上的硬件模块的操作。控制通过控制单元提供，控制单元通常遍历与用户数据单元相同的数据路径，并且至少在数据交换机内通常符合用户数据单元的格式。控制处理器和硬件模块都能够产生控制单元并将其发送到目标，即控制处理器或硬件模块。

7. 发明授权

US07061860B1 Network traffic shaping 有权
标题翻译：网络流量整形
公开(公告)号：US07061860B1
公开(公告)日：2006-06-13
申请号：US09706969
申请日：2000-11-06
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： A method for shaping network traffic in a computer network is described for packet data networks. The method includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：针对分组数据网络描述了一种用于整形计算机网络中的网络流量的方法。该方法包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

8. 发明授权

US5768273A Method and apparatus for priority level queueing in processing ATM cell header and payload 失效
标题翻译：处理ATM信元头和有效载荷的优先级排队的方法和装置
公开(公告)号：US5768273A
公开(公告)日：1998-06-16
申请号：US547828
申请日：1995-11-01
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/931 , H04L12/935 , H04J3/22
CPC分类号： H04L49/30 , H04L49/205 , H04L49/3009
摘要： An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.
摘要翻译： ATM交换机包括具有输入端口和/或输出端口的一个或多个适配器，以及用于将在输入端口处接收的异步传输模式（ATM）单元切换到输出端口的交换结构。为了保持交换机吞吐量，小区被分类为实时（高优先级）或非实时（较低优先级）小区。使用第一组信元处理逻辑以至少等于在输入端口上接收信元的速率的速率处理高优先级信元。仅当不处理高优先级单元时，才使用第二组单元处理逻辑来处理低优先级单元。

9. 发明授权

US5684797A ATM cell multicasting method and apparatus 失效
标题翻译： ATM信元多播方法及装置
公开(公告)号：US5684797A
公开(公告)日：1997-11-04
申请号：US548030
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/18 , H04L12/931 , H04L12/935 , H04L12/56
CPC分类号： H04L49/201 , H04L49/30
摘要： A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.
摘要翻译：描述了用于异步传输模式（ATM）交换机的多播设备和方法，其使用附接到每个输出ATM信元的单个目标端口（TP）向量。目标端口向量包含单元必须发送到的每个端口的标识符。在小区的传输之后，从TP向量中删除与各目标端口有关的标识符。因此，TP向量仅包含小区尚未被发送到的目标端口的标识符。当TP向量不包含标识符时，传输期间存储ATM信元的存储位置被释放用于另一小区。单播和多播流量处理相同。

10. 发明授权

US5557266A System for cascading data switches in a communication node 失效
标题翻译：用于在通信节点中级联数据交换机的系统
公开(公告)号：US5557266A
公开(公告)日：1996-09-17
申请号：US206363
申请日：1994-03-07
申请人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
发明人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
IPC分类号： H04L12/933 , H04L12/935 , H04L12/937 , H04L29/00 , H03K17/00
CPC分类号： H04L49/15 , H04L29/00 , H04L49/103 , H04L49/254 , H04L49/3027
摘要： A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.
摘要翻译：用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。类似的接口将每个适配器连接到交换机。系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

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