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1. 发明授权

US06910092B2 Chip to chip interface for interconnecting chips 失效
标题翻译：用于互连芯片的芯片到芯片接口
公开(公告)号：US06910092B2
公开(公告)日：2005-06-21
申请号：US10016800
申请日：2001-12-10
申请人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
发明人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
IPC分类号： G06F13/00 , G06F13/14 , G06F13/42
CPC分类号： G06F13/4265
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
摘要翻译：网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。可选的调度器芯片耦合到数据流芯片。命名的组件被复制以创建对称的入口和出口结构。芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

2. 发明授权

US06996650B2 Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus 失效
标题翻译：用于实现点对点总线的多个可配置子总线的方法和装置
公开(公告)号：US06996650B2
公开(公告)日：2006-02-07
申请号：US10147682
申请日：2002-05-16
申请人： Jean Calvignac , Marco Heddes , Kerry Christopher Imming , Christopher Jon Johnson , Joseph Franklin Logan , Tolga Ozguner
发明人： Jean Calvignac , Marco Heddes , Kerry Christopher Imming , Christopher Jon Johnson , Joseph Franklin Logan , Tolga Ozguner
IPC分类号： G06F13/42 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4273 , G06F13/4059
摘要： A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.
摘要翻译：提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。发送缓冲区提供发送源和串行器之间的异步接口。串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

3. 发明授权

US08170024B2 Implementing pointer and stake model for frame alteration code in a network processor 失效
标题翻译：在网络处理器中实现帧更改代码的指针和投注模型
公开(公告)号：US08170024B2
公开(公告)日：2012-05-01
申请号：US11934810
申请日：2007-11-05
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。为选择用于发送的分组提供当前指针和分支。保持当前指针用于跟踪分组中帧更改操作的当前位置。保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

4. 发明授权

US07330478B2 Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor 失效
标题翻译：方法，装置和计算机程序产品，用于实现网络处理器中帧改变代码的指针和投注模型
公开(公告)号：US07330478B2
公开(公告)日：2008-02-12
申请号：US10667024
申请日：2003-09-18
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56 , G06F15/16
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。为选择用于发送的分组提供当前指针和分支。保持当前指针用于跟踪分组中帧更改操作的当前位置。保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

5. 发明授权

US07757006B2 Implementing conditional packet alterations based on transmit port 失效
标题翻译：基于发送端口实现条件数据包更改
公开(公告)号：US07757006B2
公开(公告)日：2010-07-13
申请号：US12275241
申请日：2008-11-21
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

6. 发明授权

US06880026B2 Method and apparatus for implementing chip-to-chip interconnect bus initialization 失效
标题翻译：用于实现芯片到芯片互连总线初始化的方法和装置
公开(公告)号：US06880026B2
公开(公告)日：2005-04-12
申请号：US10147615
申请日：2002-05-16
申请人： Kerry Christopher Imming , Christopher Jon Johnson , Tolga Ozguner
发明人： Kerry Christopher Imming , Christopher Jon Johnson , Tolga Ozguner
IPC分类号： G06F13/42
CPC分类号： G06F13/4273
摘要： A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized. Once link synchronization is established, the source transmits configuration information to the destination using normal bus messages. Programmable delay elements and configuration registers are set.
摘要翻译：提供了一种用于实现芯片到芯片互连总线初始化的方法和装置。芯片到芯片互连总线包括用于两芯片之间的全双工通信的第一和第二单向总线。在初始化过程中使用低于正常总线频率。源的发送初始化定序器在所连接的单向总线上发送预定义的SYNC符号。目标芯片的接收初始化定序器检查定义数量的有效SYNC或IDLE符号。当目的地的接收初始化定序器检测到有效的SYNC或IDLE符号的定义数量时，接收初始化定序器触发目的地的发送初始化定序器，以在连接的单向总线上发送空闲符号。发送的IDLE符号由源处的接收初始化定序器检测，指示互连总线的两端同步。一旦建立了链路同步，则源使用正常总线消息将配置信息发送到目的地。可编程延迟元件和配置寄存器被设置。

7. 发明申请

US20090144452A1 IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT 失效
标题翻译：基于发送端口实现条件分组替换
公开(公告)号：US20090144452A1
公开(公告)日：2009-06-04
申请号：US12275241
申请日：2008-11-21
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

8. 发明授权

US07475161B2 Implementing conditional packet alterations based on transmit port 失效
标题翻译：基于发送端口实现条件数据包更改
公开(公告)号：US07475161B2
公开(公告)日：2009-01-06
申请号：US10655054
申请日：2003-09-04
申请人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
发明人： Kerry Christopher Imming , John David Irish , Tolga Ozguner , Andrew Henry Wottreng
IPC分类号： G06F15/16 , H04Q11/00
CPC分类号： H04L69/22
摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。提供了一种用于实现数据包更改的选择机制。与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。选择机制响应于应用的帧改变指令序列和与分组相关联的端口号，对发送的分组进行改变。选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。

9. 发明授权

US07925823B2 Reuse of functional data buffers for pattern buffers in XDR DRAM 失效
标题翻译：在XDR DRAM中重用图形缓冲区的功能数据缓冲区
公开(公告)号：US07925823B2
公开(公告)日：2011-04-12
申请号：US11875469
申请日：2007-10-19
申请人： Mark David Bellows , Kent Harold Haselhorst , Paul Allen Ganfield , Tolga Ozguner
发明人： Mark David Bellows , Kent Harold Haselhorst , Paul Allen Ganfield , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/028
摘要： A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.
摘要翻译：提供了重用功能数据缓冲器的机制。使用极限数据速率（XDR™）动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。然而，发送和接收校准有不同的程序和要求。因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

10. 发明授权

US07752379B2 Managing write-to-read turnarounds in an early read after write memory system 有权
标题翻译：在写入内存系统之后的早期读取中管理写入阅读的周转时间
公开(公告)号：US07752379B2
公开(公告)日：2010-07-06
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

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