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1. 发明申请

US20070123024A1 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing 失效
标题翻译：消除后引线键合芯片中的IMC裂纹：在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
公开(公告)号：US20070123024A1
公开(公告)日：2007-05-31
申请号：US11290087
申请日：2005-11-30
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48724 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
摘要翻译：减少或消除引线接合部件中的IMC裂纹问题的不同方法，包括：改变为顶部R 1和R 2的更多的压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

2. 发明授权

US07531442B2 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing 失效
标题翻译：消除后引线键合芯片中的IMC裂纹：在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
公开(公告)号：US07531442B2
公开(公告)日：2009-05-12
申请号：US11290087
申请日：2005-11-30
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
IPC分类号： H01L21/44
CPC分类号： H01L21/76801 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48724 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
摘要翻译：减少或消除电线接合部件中IMC裂纹问题的不同方式，包括：更换为顶部，R1和R2的更多压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

3. 发明授权

US06486002B1 Tape design to reduce warpage 有权
标题翻译：胶带设计减少翘曲
公开(公告)号：US06486002B1
公开(公告)日：2002-11-26
申请号：US09894718
申请日：2001-06-27
申请人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
发明人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
IPC分类号： H01L2144
CPC分类号： H01L23/4985 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.
摘要翻译：公开了用于半导体封装的改进的带基片设计。带衬底半导体封装包括多个管芯焊盘，多个通孔和在管芯焊盘和通孔之间互连的金属迹线图案，以在带基片上形成电路。根据本发明的方法和装置，在电路处添加额外的金属层以增加带基材的刚性，从而减少翘曲而不增加带基材封装的厚度。

4. 发明申请

US20130125199A1 TESTING ACCESS POLICIES 有权
标题翻译：测试访问政策
公开(公告)号：US20130125199A1
公开(公告)日：2013-05-16
申请号：US13294162
申请日：2011-11-10
申请人： Mark F. Novak , Paul Leach , Vishal Agarwal , David McPherson , Sunil Gottumukkala , Jignesh Shah , Arun K. Nanda , Nir Ben Zvi , Pranav Kukreja , Ramaswamy Ranganathan
发明人： Mark F. Novak , Paul Leach , Vishal Agarwal , David McPherson , Sunil Gottumukkala , Jignesh Shah , Arun K. Nanda , Nir Ben Zvi , Pranav Kukreja , Ramaswamy Ranganathan
IPC分类号： G06F21/00
CPC分类号： G06Q10/04 , G06Q50/26
摘要： A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.
摘要翻译：管理对资源的访问的策略可以在被用于控制对资源的访问之前被针对真实的访问请求进行测试。在一个示例中，对资源的访问受政策管辖，被称为有效策略。当修改或更换策略时，修改或替换可能成为测试策略。当请求访问资源时，可以根据有效策略和测试策略对请求进行评估。是否授予访问是根据有效策略确定的，但是将根据测试策略作出的决定被注明，并可能被记录。如果测试策略在面对现实访问请求时被确定为可接受的行为，则可以用测试策略替换当前的有效策略。

5. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

6. 发明授权

US06798035B1 Bonding pad for low k dielectric 有权
标题翻译：低k电介质接合垫
公开(公告)号：US06798035B1
公开(公告)日：2004-09-28
申请号：US10600255
申请日：2003-06-20
申请人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
发明人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
IPC分类号： H01L3100
CPC分类号： H01L24/05 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.
摘要翻译：一种具有导电覆盖层的焊盘结构。导电的第一支撑层设置在导电覆盖层的正下方，在导电覆盖层和导电的第一支撑层之间没有任何中间层。导电性第一支撑层被构造为没有空隙的片材之一和在第一方向上具有开槽空隙的片材。导电的第二支撑层设置在导电的第一支撑层之下。导电性第二支撑层被构造为在第一方向上具有开槽空隙的片材之一，在第二方向上具有开槽空隙的片材和具有棋盘空隙的片材。

7. 发明授权

US06991147B2 Insulated bonding wire tool for microelectronic packaging 失效
标题翻译：用于微电子封装的绝缘接合线工具
公开(公告)号：US06991147B2
公开(公告)日：2006-01-31
申请号：US10642706
申请日：2003-08-18
申请人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
IPC分类号： B23K31/02 , B05D5/12
CPC分类号： H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/8502 , H01L2224/85181 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01079 , H01L2924/20753 , H01L2924/06 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
摘要翻译：一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

8. 发明授权

US06781150B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06781150B2
公开(公告)日：2004-08-24
申请号：US10229601
申请日：2002-08-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L2358
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

9. 发明授权

US5457880A Embedded features for monitoring electronics assembly manufacturing processes 失效
标题翻译：用于监控电子组件制造工艺的嵌入式功能
公开(公告)号：US5457880A
公开(公告)日：1995-10-17
申请号：US193330
申请日：1994-02-08
申请人： Philip E. McKinley , Carl J. Bloch , Ramaswamy Ranganathan
发明人： Philip E. McKinley , Carl J. Bloch , Ramaswamy Ranganathan
IPC分类号： G01N13/02 , H05K1/02 , H05K3/12 , H05K3/34 , H05K3/30
CPC分类号： H05K3/1216 , H05K1/0269 , H05K3/3484 , G01N2013/0225 , H05K2201/09063 , H05K2201/09781 , H05K2203/043 , H05K2203/161 , H05K2203/163 , H05K2203/168 , Y10T29/49131 , Y10T29/49133 , Y10T29/49144
摘要： Cooperative patterns are formed in stencils and/or substrates that facilitate the monitoring and control of the circuit assembly process. A pattern of successively-larger etch blocks receives a corresponding pattern of same-size solder blocks; solder reflow problems are indicated when either too many or too few etch blocks are completely covered by solder after reflow. A pattern of same-size etch blocks receives a corresponding pattern of successively-larger solder blocks; problems with solder stencil clogging are indicated when smaller ones of the etch blocks do not receive solder paste during stenciling. Finally, component beacon openings or translucent areas are made in the electronics assembly at component locations. After component placement, the board is appropriately lit, and any uncovered openings indicate missing or grossly misaligned components.
摘要翻译：辅助图案形成在便于监测和控制电路组装过程的模板和/或基板中。连续更大的蚀刻块的图案接收相同尺寸的焊料块的相应图案; 当在回流之后太多或太少的蚀刻块被焊料完全覆盖时，表明了焊料回流问题。相同尺寸的蚀刻块的图案接收相应的连续更大的焊料块的图案; 当较小的蚀刻块在模版期间不接收焊膏时，会显示焊锡模板堵塞的问题。最后，在组件位置处的电子组件中制造组件信标开口或半透明区域。在组件放置之后，板子被适当地点亮，并且任何未覆盖的开口指示丢失或严重不对准的部件。

10. 发明授权

US08813170B2 Testing access policies 有权
标题翻译：测试访问策略
公开(公告)号：US08813170B2
公开(公告)日：2014-08-19
申请号：US13294162
申请日：2011-11-10
申请人： Mark F. Novak , Paul Leach , Vishal Agarwal , David McPherson , Sunil Gottumukkala , Jignesh Shah , Arun K. Nanda , Nir Ben Zvi , Pranav Kukreja , Ramaswamy Ranganathan
发明人： Mark F. Novak , Paul Leach , Vishal Agarwal , David McPherson , Sunil Gottumukkala , Jignesh Shah , Arun K. Nanda , Nir Ben Zvi , Pranav Kukreja , Ramaswamy Ranganathan
IPC分类号： G06F17/00
CPC分类号： G06Q10/04 , G06Q50/26
摘要： A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.
摘要翻译：管理对资源的访问的策略可以在被用于控制对资源的访问之前被针对真实的访问请求进行测试。在一个示例中，对资源的访问受政策管辖，被称为有效策略。当修改或更换策略时，修改或替换可能成为测试策略。当请求访问资源时，可以根据有效策略和测试策略对请求进行评估。是否授予访问是根据有效策略确定的，但是将根据测试策略作出的决定被注明，并可能被记录。如果测试策略在面对现实访问请求时被确定为可接受的行为，则可以用测试策略替换当前的有效策略。

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