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1. 发明授权

US06289496B1 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards 失效
标题翻译：将输入输出设计对象放置在支持多个电压标准的可编程门阵列中
公开(公告)号：US06289496B1
公开(公告)日：2001-09-11
申请号：US09107022
申请日：1998-06-29
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： H03K19/17744 , G06F17/5072 , H03K19/17788
摘要： A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同电压标准的输入输出（I / O）设计对象的可编程门阵列中的方法和装置。可编程门阵列具有多个位置，其布置成支撑具有多个不同输入和输出电压标准的接口的支架。在示例性实施例中，I / O设计对象通过首先执行模拟退火而被放置在可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的设计对象电压标准之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，则基于先前的布局结果将标准分配给银行，并重复二分配匹配过程。

2. 发明授权

US06625795B1 Method and apparatus for placement of input-output design objects into a programmable gate array 有权
标题翻译：用于将输入输出设计对象放置到可编程门阵列中的方法和装置
公开(公告)号：US06625795B1
公开(公告)日：2003-09-23
申请号：US09866052
申请日：2001-05-25
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , H03K19/17744
摘要： A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同I / O属性的I / O设计对象的可编程门阵列中的方法和装置。 I / O设计对象的I / O属性定义了设计对象的电气特性。可编程门阵列具有布置成支持各种电接口特性的单元的多个位置（IOB）。在示例实施例中，I / O设计对象通过首先执行模拟退火而被放置到可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的I / O设计对象的I / O属性之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，那么根据先前的放置结果，将一组I / O属性分配给存储体，并重复二分配匹配过程。

3. 发明授权

US06484298B1 Method and apparatus for automatic timing-driven implementation of a circuit design 有权
标题翻译：自动定时驱动实现电路设计的方法和装置
公开(公告)号：US06484298B1
公开(公告)日：2002-11-19
申请号：US09574641
申请日：2000-05-18
申请人： Sudip K. Nag , Kamal Chaudhary , Jason H. Anderson , Madabhushi V. R. Chari , Sandor S. Kalman
发明人： Sudip K. Nag , Kamal Chaudhary , Jason H. Anderson , Madabhushi V. R. Chari , Sandor S. Kalman
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.
摘要翻译：一种用于电路设计的自动定时驱动实现的方法和装置。在一个实施例中，使用在每次迭代中自动和动态生成的时序约束来迭代地执行实现电路设计的不同阶段。该过程有助于确定并实现实施设计的最高性能水平。在另一个实施例中，使用所选数量的关键连接来动态地改变时序约束。通常，从电路设计中自动选择多个连接，并用于导出将在下一次迭代中应用的新的时序约束。与设计中的路径相关联的松弛值也用于推导新的时序约束。

4. 发明授权

US06877040B1 Method and apparatus for testing routability 有权
标题翻译：用于测试可布线性的方法和装置
公开(公告)号：US06877040B1
公开(公告)日：2005-04-05
申请号：US09624716
申请日：2000-07-25
申请人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
发明人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
IPC分类号： G06F15/173
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.
摘要翻译：一种用于确定多个网络的路由可行性的方法和装置。每个网络具有一组或多个路由解决方案，其中每个解决方案指定网络所消耗的一个或多个路由资源。生成具有表示相应的净/解对对的变量的活力布尔函数。如果存在一组变量的值，使得每个网络的至少一个变量在逻辑上为真，那么活动函数为真。使用表示网络/解决方案对的变量生成排他性功能。如果存在变量的至少一组值，使得没有资源被使用超过预定数量的网络，则排他性功能是真实的。如果有一组变量的值，使用提供的解决方案，网络可以路由，以使活动和排他性功能都是真实的。

5. 发明授权

US07725868B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07725868B1
公开(公告)日：2010-05-25
申请号：US11983550
申请日：2007-11-09
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

6. 发明授权

US07306977B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07306977B1
公开(公告)日：2007-12-11
申请号：US10651808
申请日：2003-08-29
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

7. 发明授权

US06983439B1 Unified placer infrastructure 有权
标题翻译：统一铺设基础设施
公开(公告)号：US06983439B1
公开(公告)日：2006-01-03
申请号：US10283638
申请日：2002-10-29
申请人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
发明人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F9/45
CPC分类号： G06F17/5072
摘要： Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
摘要翻译：描述了用于将设计对象放置在诸如包括FPGA的可编程逻辑器件的阵列架构上的放置器系统的方法和装置。更具体地，描述了用于与放置器芯通信的放置器接口。放置接口从外部实体接收信息，并统一并概括了该信息的堆栈核心。外部实体包括架构，设计，设备，约束和算法规定的可移动物体的不同表示。

8. 发明授权

US07398496B1 Unified placer infrastructure 有权
标题翻译：统一铺设基础设施
公开(公告)号：US07398496B1
公开(公告)日：2008-07-08
申请号：US11242539
申请日：2005-09-30
申请人： James L. Saunders , Krishnan Anandh , Guenther Stenz , Sudip K. Nag , Jason H. Anderson
发明人： James L. Saunders , Krishnan Anandh , Guenther Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
摘要翻译：描述了用于将设计对象放置在诸如包括FPGA的可编程逻辑器件的阵列架构上的放置器系统的方法和装置。更具体地，描述了用于与放置器芯通信的放置器接口。放置接口从外部实体接收信息，并统一并概括了该信息的堆栈核心。外部实体包括架构，设计，设备，约束和算法规定的可移动物体的不同表示。

9. 发明授权

US07143380B1 Method for application of network flow techniques under constraints 有权
标题翻译：网络流技术在约束条件下的应用方法
公开(公告)号：US07143380B1
公开(公告)日：2006-11-28
申请号：US10215979
申请日：2002-08-08
申请人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
发明人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/509 , G06F2217/06
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

10. 发明授权

US07240315B1 Automated local clock placement for FPGA designs 有权
标题翻译： FPGA设计的自动本地时钟放置
公开(公告)号：US07240315B1
公开(公告)日：2007-07-03
申请号：US10651789
申请日：2003-08-29
申请人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
发明人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/08 , G06F2217/62
摘要： A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.
摘要翻译：将本地时钟网放置在电路设计中的方法（500）可以包括识别用于电路设计的本地时钟网络并且选择对应于每个本地时钟网络的组件（510,515），以及将初始位置分配给本地时钟网络的每个组件（520）。该方法还可以包括生成至少一个成本函数（530,550）以评估（555）本地时钟网络的组件的不同放置。可以使用一个或多个成本函数对本地时钟网（205）的组件（220,240）进行退火（535-575），以将位置分配给本地时钟网络的每个组件。

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