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1. 发明授权

US06625795B1 Method and apparatus for placement of input-output design objects into a programmable gate array 有权
标题翻译：用于将输入输出设计对象放置到可编程门阵列中的方法和装置
公开(公告)号：US06625795B1
公开(公告)日：2003-09-23
申请号：US09866052
申请日：2001-05-25
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , H03K19/17744
摘要： A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同I / O属性的I / O设计对象的可编程门阵列中的方法和装置。 I / O设计对象的I / O属性定义了设计对象的电气特性。可编程门阵列具有布置成支持各种电接口特性的单元的多个位置（IOB）。在示例实施例中，I / O设计对象通过首先执行模拟退火而被放置到可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的I / O设计对象的I / O属性之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，那么根据先前的放置结果，将一组I / O属性分配给存储体，并重复二分配匹配过程。

2. 发明授权

US06289496B1 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards 失效
标题翻译：将输入输出设计对象放置在支持多个电压标准的可编程门阵列中
公开(公告)号：US06289496B1
公开(公告)日：2001-09-11
申请号：US09107022
申请日：1998-06-29
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： H03K19/17744 , G06F17/5072 , H03K19/17788
摘要： A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同电压标准的输入输出（I / O）设计对象的可编程门阵列中的方法和装置。可编程门阵列具有多个位置，其布置成支撑具有多个不同输入和输出电压标准的接口的支架。在示例性实施例中，I / O设计对象通过首先执行模拟退火而被放置在可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的设计对象电压标准之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，则基于先前的布局结果将标准分配给银行，并重复二分配匹配过程。

3. 发明授权

US07398496B1 Unified placer infrastructure 有权
标题翻译：统一铺设基础设施
公开(公告)号：US07398496B1
公开(公告)日：2008-07-08
申请号：US11242539
申请日：2005-09-30
申请人： James L. Saunders , Krishnan Anandh , Guenther Stenz , Sudip K. Nag , Jason H. Anderson
发明人： James L. Saunders , Krishnan Anandh , Guenther Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
摘要翻译：描述了用于将设计对象放置在诸如包括FPGA的可编程逻辑器件的阵列架构上的放置器系统的方法和装置。更具体地，描述了用于与放置器芯通信的放置器接口。放置接口从外部实体接收信息，并统一并概括了该信息的堆栈核心。外部实体包括架构，设计，设备，约束和算法规定的可移动物体的不同表示。

4. 发明授权

US06983439B1 Unified placer infrastructure 有权
标题翻译：统一铺设基础设施
公开(公告)号：US06983439B1
公开(公告)日：2006-01-03
申请号：US10283638
申请日：2002-10-29
申请人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
发明人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F9/45
CPC分类号： G06F17/5072
摘要： Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
摘要翻译：描述了用于将设计对象放置在诸如包括FPGA的可编程逻辑器件的阵列架构上的放置器系统的方法和装置。更具体地，描述了用于与放置器芯通信的放置器接口。放置接口从外部实体接收信息，并统一并概括了该信息的堆栈核心。外部实体包括架构，设计，设备，约束和算法规定的可移动物体的不同表示。

5. 发明授权

US07240315B1 Automated local clock placement for FPGA designs 有权
标题翻译： FPGA设计的自动本地时钟放置
公开(公告)号：US07240315B1
公开(公告)日：2007-07-03
申请号：US10651789
申请日：2003-08-29
申请人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
发明人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/08 , G06F2217/62
摘要： A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.
摘要翻译：将本地时钟网放置在电路设计中的方法（500）可以包括识别用于电路设计的本地时钟网络并且选择对应于每个本地时钟网络的组件（510,515），以及将初始位置分配给本地时钟网络的每个组件（520）。该方法还可以包括生成至少一个成本函数（530,550）以评估（555）本地时钟网络的组件的不同放置。可以使用一个或多个成本函数对本地时钟网（205）的组件（220,240）进行退火（535-575），以将位置分配给本地时钟网络的每个组件。

6. 发明授权

US07313778B1 Method system and apparatus for floorplanning programmable logic designs 有权
标题翻译：用于布局规划可编程逻辑设计的方法系统和装置
公开(公告)号：US07313778B1
公开(公告)日：2007-12-25
申请号：US10787326
申请日：2004-02-26
申请人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
发明人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.
摘要翻译：设计可编程逻辑器件的方法（600）可以包括以下步骤：识别损害不适合于可编程逻辑器件（605）并且限定具有相同类型的部件的模块（615）的电路设计的平面图的成本函数）。可以确定与模块相关联的一组形状（610）。电路设计可以退火（620），以使用成本函数和模块的形状集来确定平面图。

7. 发明授权

US06754878B1 Recognizing structure information from a netlist 有权
标题翻译：从网表识别结构信息
公开(公告)号：US06754878B1
公开(公告)日：2004-06-22
申请号：US10402444
申请日：2003-03-27
申请人： Guenter Stentz , James L. Saunders
发明人： Guenter Stentz , James L. Saunders
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Method and apparatus for recognizing data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.
摘要翻译：用于识别网表中的数据路径结构的方法和装置。识别网表中的各个阶段。每个阶段包括一组处理多个位的组件。连接舞台的公共汽车也被识别。生成图表来表示阶段和总线。图中的顶点表示阶段，边缘表示总线。该图被分成具有表示存储元件的终止顶点的子图。每个子图表示数据路径结构。

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