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1. 发明授权

US6001730A Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers 失效
标题翻译：用于抛光使用钽基阻挡层的铜互连的化学机械抛光（CMP）浆料
公开(公告)号：US6001730A
公开(公告)日：1999-12-14
申请号：US954191
申请日：1997-10-20
申请人： Janos Farkas , Rajeev Bajaj , Melissa Freeman , David K. Watts , Sanjit Das
发明人： Janos Farkas , Rajeev Bajaj , Melissa Freeman , David K. Watts , Sanjit Das
IPC分类号： C09G1/02 , H01L21/321 , H01L21/768 , H01L1/00
CPC分类号： H01L21/76873 , C09G1/02 , H01L21/3212 , H01L21/7684 , H01L21/76843 , H01L21/76877
摘要： A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).
摘要翻译：在集成电路（IC）上形成铜互连的方法通过形成具有开口的电介质层（20）开始。在层（20）的开口内形成有TaN或TaSiN等钽系阻挡层（21）。在阻挡层（21）的上方形成铜层（22）。第一CMP工艺用于抛光铜（22）以暴露阻挡层（21）的部分。然后使用与第一CMP工艺不同的第二CMP工艺来比电介质层（20）或铜层（22）更快地抛光层（21）的暴露部分。在该两步CMP工艺之后，跨越集成电路基板（12）形成具有钽基阻挡层的铜互连。

2. 发明授权

US5897375A Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture 失效
标题翻译：用于铜的化学机械抛光（CMP）浆料和集成电路制造中的使用方法
公开(公告)号：US5897375A
公开(公告)日：1999-04-27
申请号：US954190
申请日：1997-10-20
申请人： David Watts , Rajeev Bajaj , Sanjit Das , Janos Farkas , Chelsea Dang , Melissa Freeman , Jaime A. Saravia , Jason Gomez , Lance B. Cook
发明人： David Watts , Rajeev Bajaj , Sanjit Das , Janos Farkas , Chelsea Dang , Melissa Freeman , Jaime A. Saravia , Jason Gomez , Lance B. Cook
IPC分类号： B24B37/00 , C09G1/02 , C09K3/14 , H01L21/304 , B24B1/00
CPC分类号： C23F3/00 , C09G1/02 , C09K3/1463 , C09K3/1472
摘要： A method for chemical mechanical polishing (CMP) a copper layer (22) begins by forming the copper layer (22). The copper layer (22) is then exposed to a slurry (24). The slurry (24) contains an oxidizing agent such as H.sub.2 O.sub.2, a carboxylate salt such as ammonium citrate, an abrasive slurry such as alumna abrasive, an optional triazole or triazole derivative, and a remaining balance of a solvent such as deionized water. The use of the slurry (24) polishes the copper layer (22) with a high rate of removal whereby pitting and corrosion of the copper layer (22) is reduced and good copper interconnect planarity is achieved. This slurry (24) has good selectivity of copper to oxide, and results in copper devices which have good electrical performance. In addition, disposal of the slurry (24) is not environmentally difficult since the slurry (24) is environmentally sound when compared to other prior art slurries.
摘要翻译：通过形成铜层（22）开始化学机械抛光（CMP）铜层（22）的方法。然后将铜层（22）暴露于浆料（24）。浆料（24）含有氧化剂如H 2 O 2，羧酸盐如柠檬酸铵，研磨浆如校准研磨剂，任选的三唑或三唑衍生物，剩余的溶剂如去离子水。浆料（24）的使用以高的去除速度抛光铜层（22），从而降低了铜层（22）的点蚀和腐蚀，并实现了良好的铜互连平面性。这种浆料（24）具有铜对氧化物的良好选择性，并且导致具有良好电性能的铜器件。此外，浆料（24）的处理不是环境困难的，因为与其它现有技术的浆料相比，浆料（24）是无害环境的。

3. 发明授权

US5882243A Method for polishing a semiconductor wafer using dynamic control 失效
标题翻译：使用动态控制来研磨半导体晶片的方法
公开(公告)号：US5882243A
公开(公告)日：1999-03-16
申请号：US839996
申请日：1997-04-24
申请人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
发明人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
IPC分类号： B24B37/005 , B24B49/04 , B24B51/00
CPC分类号： B24B37/005 , B24B49/04
摘要： A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.
摘要翻译：根据本发明，抛光系统（10）用于抛光半导体晶片（16）。抛光系统（10）包括包括调制单元（20）的晶片载体（14）。调制单元（20）包括由柔性下板（22）和多个较小的上板段（24）组成的多个电容器。控制器（40）监测每个较小的上板段（24）和下板（22）之间的电容，并将测量的电容与预定的设定电容进行比较。在测量电容和预定电容不同的程度上，控制器（40）调节施加到相应的上板段（24）的电压，使得所测量的电容和预定电容对齐。因此，本发明能够在抛光时实现晶片的形状的动态和局部控制。

4. 发明授权

US06204169B1 Processing for polishing dissimilar conductive layers in a semiconductor device 失效
标题翻译：用于在半导体器件中抛光不同导电层的处理
公开(公告)号：US06204169B1
公开(公告)日：2001-03-20
申请号：US08822025
申请日：1997-03-24
申请人： Rajeev Bajaj , Janos Farkas , Sung C. Kim , Jaime Saravia
发明人： Rajeev Bajaj , Janos Farkas , Sung C. Kim , Jaime Saravia
IPC分类号： H01L214763
CPC分类号： H01L21/3212
摘要： A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different urce containers (111 and 112), wherein the first slurry is dispensed until e tungsten is removed and then the slurry dispense is switched to second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.
摘要翻译：抛光沉积在半导体器件衬底上的两种不同导电材料的工艺可以独立地优化每个导电材料的抛光，同时利用相同的抛光设备来制造效率。使用一个抛光机（10），但是使用两种不同的浆料配方来抛光半导体器件基板（250）的钨层（258）和钛层（256）。两个浆料可以从两个不同的容器（111和112）顺序地分配到相同的抛光平台（132）上，其中分配第一浆料直到除去钨，然后将浆料分配切换到第二浆料以除去钛。在优选的实施方案中，第一浆料组合物是硝酸铁浆料，而第二浆料组合物是草酸浆料。

5. 发明授权

US5985755A Processing for polishing dissimilar conductive layers in a semiconductor device 失效
标题翻译：用于在半导体器件中抛光不同导电层的处理
公开(公告)号：US5985755A
公开(公告)日：1999-11-16
申请号：US822025
申请日：1997-03-24
申请人： Rajeev Bajaj , Janos Farkas , Sung C. Kim , Jaime Saravia
发明人： Rajeev Bajaj , Janos Farkas , Sung C. Kim , Jaime Saravia
IPC分类号： H01L21/304 , H01L21/321 , H01L21/4763
CPC分类号： H01L21/3212
摘要： A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.
摘要翻译：抛光沉积在半导体器件衬底上的两种不同导电材料的工艺可以独立地优化每个导电材料的抛光，同时利用相同的抛光设备来制造效率。使用一个抛光机（10），但是使用两种不同的浆料配方来抛光半导体器件基板（250）的钨层（258）和钛层（256）。两个浆料可以从两个不同的源容器（111和112）顺序地分配到相同的抛光平台（132）上，其中分配第一浆料直到除去钨，然后将浆料分配切换到第二浆料以除去的钛。在优选的实施方案中，第一浆料组合物是硝酸铁浆料，而第二浆料组合物是草酸浆料。

6. 发明授权

US6045435A Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects 失效
标题翻译：用于集成电路金属互连的低选择性化学机械抛光（CMP）工艺
公开(公告)号：US6045435A
公开(公告)日：2000-04-04
申请号：US905757
申请日：1997-08-04
申请人： Rajeev Bajaj , Subramoney Iyer , Thom Kobayashi , Jaime Saravia , Mark Fernandes , David K. Watts
发明人： Rajeev Bajaj , Subramoney Iyer , Thom Kobayashi , Jaime Saravia , Mark Fernandes , David K. Watts
IPC分类号： B24B37/04 , B24D13/14 , H01L21/321 , H01L21/768 , B24B1/00
CPC分类号： B24B37/24 , B24B37/042 , B24B37/26 , H01L21/3212 , H01L21/7684
摘要： A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along with slurry (22) containing silica and an acidic based oxidizer such as oxadic acid in a chemical mechanical polishing (CMP) process. The result is less than 5:1 and preferably 1:1. This low selectivity results in the metal layer (20) being polished to a level below the surface of the surrounding oxide in a timed-controlled polish.
摘要翻译：示出了用于抛光包含宽特征（12），低密度特征（14）和高密度特征（18）的组合的金属层（20）的方法。在化学机械抛光（CMP）工艺中，与含有二氧化硅和酸性氧化剂如草酸的浆料（22）一起使用具有大于50的肖氏D硬度的亲水抛光垫（24）。结果小于5：1，优选为1：1。这种低选择性导致金属层（20）以定时控制的抛光剂抛光到周围氧化物表面以下的水平。

7. 发明授权

US6071816A Method of chemical mechanical planarization using a water rinse to prevent particle contamination 失效
标题翻译：使用水冲洗的化学机械平面化方法以防止颗粒污染
公开(公告)号：US6071816A
公开(公告)日：2000-06-06
申请号：US921131
申请日：1997-08-29
申请人： David K. Watts , Rajeev Bajaj , Sanjit K. Das
发明人： David K. Watts , Rajeev Bajaj , Sanjit K. Das
IPC分类号： H01L21/304 , H01L21/321 , H01L21/302
CPC分类号： H01L21/32115
摘要： A method of chemical mechanical planarization of a semiconductor device provides a semiconductor device having a device front surface and a device back surface with the device front surface being a top surface of a second metal layer. A first planarizing step planarizes the device front surface with a first medium to expose a device second front surface, where the first medium comprises a first abrasive component and a first chemical solution. A rinsing step then rinses the device back surface with water. A second planarizing step then planarizes the device second front surface with a second medium where the second medium comprises a second abrasive component and a second chemical solution.
摘要翻译：半导体器件的化学机械平坦化的方法提供了具有器件正面和器件背面的半导体器件，器件前表面是第二金属层的顶表面。第一平面化步骤用第一介质平坦化装置前表面以暴露装置第二前表面，其中第一介质包括第一研磨部件和第一化学溶液。冲洗步骤然后用水冲洗设备背面。第二平面化步骤然后用第二介质平面化设备第二前表面，其中第二介质包括第二研磨组分和第二化学溶液。

8. 发明授权

US09162344B2 Method and apparatus for CMP conditioning 有权
标题翻译： CMP调理方法和装置
公开(公告)号：US09162344B2
公开(公告)日：2015-10-20
申请号：US13785845
申请日：2013-03-05
申请人： Rajeev Bajaj
发明人： Rajeev Bajaj
IPC分类号： B24B1/00 , B24B53/017 , B23K26/00 , B24B53/095
CPC分类号： B24B53/017 , B23K26/3576 , B24B53/095
摘要： A polishing pad conditioning apparatus includes a laser beam generating unit for providing a laser beam, a fluid delivery system for providing a fluid stream and a vacuum line for removing debris. The laser beam may directly impinge on a surface of a polishing pad thereby creating cutting action, while an atomized fluid stream provides cooling and pad debris along with fluid are removed thru the vacuum line. Alternatively, the laser beam may be combined with the atomized fluid stream in a region above the pad surface to substantially impart part of its energy to the fluid stream, generating high energy droplets which provide “cool” cutting action on the pad surface.
摘要翻译：抛光垫调节装置包括用于提供激光束的激光束产生单元，用于提供流体流的流体输送系统和用于去除碎屑的真空管线。激光束可以直接冲击抛光垫的表面，从而产生切割作用，而雾化的流体流提供冷却和垫片碎屑以及流体通过真空管线被去除。或者，激光束可以与垫表面上方的区域中的雾化流体流组合，以将其能量的一部分基本上赋予流体流，产生在焊盘表面上提供“冷”切割作用的高能量液滴。

9. 发明申请

US20150056900A1 POLISHING PAD WITH HOMOGENEOUS BODY HAVING DISCRETE PROTRUSIONS THEREON 有权
标题翻译：具有同位素分布的均质体的抛光垫
公开(公告)号：US20150056900A1
公开(公告)日：2015-02-26
申请号：US14530534
申请日：2014-10-31
申请人： Rajeev Bajaj , Ping Huang , Robert Kerprich , William C. Allison , Richard Frentzel , Diane Scott
发明人： Rajeev Bajaj , Ping Huang , Robert Kerprich , William C. Allison , Richard Frentzel , Diane Scott
IPC分类号： B24B37/26 , B29C39/12 , B24B37/24 , B24D18/00 , B24B37/20 , B24B37/22
CPC分类号： B24B37/26 , B24B37/205 , B24B37/22 , B24B37/24 , B24D18/0009 , B29C39/123 , B29K2075/00 , B29L2009/00 , B29L2031/736
摘要： Polishing pads with homogeneous bodies having discrete protrusions thereon are described. In an example, a polishing pad for polishing a substrate includes a homogeneous body having a polishing side and a back side. The homogeneous body is composed of a material having a first hardness. A plurality of discrete protrusions is disposed on and covalently bonded with the polishing side of the homogeneous body. The plurality of discrete protrusions is composed of a material having a second hardness different from the first hardness. Methods of fabricating polishing pads with homogeneous bodies having discrete protrusions thereon are also described.
摘要翻译：描述具有其上具有离散突起的均匀体的抛光垫。在一个实例中，用于抛光衬底的抛光垫包括具有抛光侧和背面的均匀体。均质体由具有第一硬度的材料构成。多个分立的突起设置在同质体的抛光侧上并与之共同地结合。多个离散突起由具有与第一硬度不同的第二硬度的材料构成。还描述了制造具有其上具有离散突起的均匀体的抛光垫的方法。

10. 发明授权

US07815778B2 Electro-chemical mechanical planarization pad with uniform polish performance 有权
标题翻译：电化学机械平面化垫具有均匀的抛光性能
公开(公告)号：US07815778B2
公开(公告)日：2010-10-19
申请号：US11562310
申请日：2006-11-21
申请人： Rajeev Bajaj
发明人： Rajeev Bajaj
IPC分类号： B23H5/06 , B23H5/08 , B23H5/10 , C25F3/16 , C25F3/18 , C25F3/30
CPC分类号： B24B37/20
摘要： A polishing pad includes at least one conductive polishing element supported by a compressible under layer having conductive patterning therein, the conductive patterning adapted to permit coupling of a potential to the conductive polishing element; a guide plate above the compressible under layer, the guide plate having a hole through which the polishing element passes and further having a cathodic element connected thereto; and a slurry distribution layer adhered to the guide plate opposite the compressible under layer. The polishing pad may further include a proton exchange membrane placed over the cathodic element. A semiconductor wafer having a metal film thereon may be polished using the polishing pad by placing the wafer in contact with the polishing element, applying anodic current to the polishing element and cathodic current to the cathodic element, and polishing with an anodic solution. For copper films, a sulfuric acid-copper sulfate solution may be used.
摘要翻译：抛光垫包括由其中具有导电图案化的可压缩底层支撑的至少一个导电抛光元件，所述导电图案适于允许将电位耦合到导电抛光元件; 在可压缩底层上方的引导板，所述引导板具有用于抛光元件通过的孔，并且还具有连接到其上的阴极元件; 以及粘附到与可压缩底层相对的引导板的浆料分布层。抛光垫还可以包括置于阴极元件上的质子交换膜。可以使用抛光垫将晶片与抛光元件接触，向抛光元件施加阳极电流，向阴极元件施加阴极电流，并用阳极溶液抛光，可以抛光其上具有金属膜的半导体晶片。对于铜膜，可以使用硫酸 - 硫酸铜溶液。

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