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1. 发明授权

US06915411B2 SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath 有权
标题翻译： SIMD处理器与矢量指针数据路径和向量计算数据通路同时运行
公开(公告)号：US06915411B2
公开(公告)日：2005-07-05
申请号：US10197733
申请日：2002-07-18
申请人： Jamie H. Moreno , Jeffrey Haskell Derby , Uzi Shvadron , Fredy Daniel Neeser , Victor Zyuban , Ayal Zaks , Shay Ben-David
发明人： Jamie H. Moreno , Jeffrey Haskell Derby , Uzi Shvadron , Fredy Daniel Neeser , Victor Zyuban , Ayal Zaks , Shay Ben-David
IPC分类号： G06F15/80
CPC分类号： G06F15/8092
摘要： A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.
摘要翻译：数字信号处理器（DSP）包括基于SIMD的组织，其中在多个单指令多数据（SIMD）数据通路或级联连接的级中执行操作。每个阶段的功能和数据值可以是不同的，包括每个阶段中不同的宽度（例如，每个值的不同位数）。通过向量指针数据路径中的向量指针寄存器间接地选择计算数据通路中的数据的操作数和目的地。每个向量指针寄存器包含多个指向计算数据路径的寄存器文件的指针。

2. 发明授权

US07017028B2 Apparatus and method for updating pointers for indirect and parallel register access 失效
标题翻译：用于更新用于间接和并行寄存器访问的指针的装置和方法
公开(公告)号：US07017028B2
公开(公告)日：2006-03-21
申请号：US10389212
申请日：2003-03-14
申请人： Shay Ben-David , Jeffrey Haskell Derby , Thomas W. Fox , Fredy Daniel Neeser , Jamie H. Moreno , Uzi Shvadron , Ayal Zaks
发明人： Shay Ben-David , Jeffrey Haskell Derby , Thomas W. Fox , Fredy Daniel Neeser , Jamie H. Moreno , Uzi Shvadron , Ayal Zaks
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G06F15/8084
摘要： An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.
摘要翻译：提供了一种用于更新用于访问多端口存储器中的一个或多个多个数据元素（即，一个或多个向量数据元素）的一个或多个多个指针（即一个或多个向量指针）的装置和方法。第一寄存器文件保存矢量指针，第二寄存器文件保存步幅数据，并且多个功能单元将来自第二寄存器堆的数据与来自第一寄存器堆的数据组合。将数据组合的结果传送到第一个寄存器文件并表示更新的向量指针。此外，提供第三寄存器文件用于保持模数选择器数据以指定用于循环寻址的循环缓冲器的大小。

3. 发明授权

US07313788B2 Vectorization in a SIMdD DSP architecture 失效
标题翻译： SIMdD DSP架构中的向量化
公开(公告)号：US07313788B2
公开(公告)日：2007-12-25
申请号：US10695970
申请日：2003-10-29
申请人： Shay Ben-David , Dorit Naishlos , Uzi Shvadron , Ayal Zaks
发明人： Shay Ben-David , Dorit Naishlos , Uzi Shvadron , Ayal Zaks
IPC分类号： G06F9/45 , G06F7/00 , G06F15/80
CPC分类号： G06F8/41
摘要： A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.
摘要翻译：一种用于确定计算机处理器架构中的向量化配置的方法，所述方法包括识别计算机程序中的可矢量化循环，识别在所述架构中实现所述循环所需的数据的存储器访问模式，计算所述资源所需的一组候选配置对架构中的数据进行向量化，其中计算步骤包括配置架构的向量指针寄存器，以支持对读取结构的重新排序使用和对该体系结构的向量元素文件进行重写顺序的使用，候选人根据预定义的选择标准，并在架构中实现所选择的向量化配置。

4. 发明申请

US20050097301A1 Vectorization in a SIMdD DSP architecture 失效
标题翻译： SIMdD DSP架构中的向量化
公开(公告)号：US20050097301A1
公开(公告)日：2005-05-05
申请号：US10695970
申请日：2003-10-29
申请人： Shay Ben-David , Dorit Naishlos , Uzi Shvadron , Ayal Zaks
发明人： Shay Ben-David , Dorit Naishlos , Uzi Shvadron , Ayal Zaks
IPC分类号： G06F9/45 , G06F15/00 , G06F15/76
CPC分类号： G06F8/41
摘要： A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.
摘要翻译：一种用于确定计算机处理器架构中的向量化配置的方法，所述方法包括识别计算机程序中的可矢量化循环，识别在所述架构中实现所述循环所需的数据的存储器访问模式，计算所述资源所需的一组候选配置对架构中的数据进行向量化，其中计算步骤包括配置架构的向量指针寄存器，以支持对读取结构的重新排序使用和对该体系结构的向量元素文件进行重写顺序的使用，候选人根据预定义的选择标准，并在架构中实现所选择的向量化配置。

5. 发明授权

US5822328A Frame synchronization mechanism for digital simultaneous voice/data modems 失效
标题翻译：数字同步语音/数据调制解调器的帧同步机制
公开(公告)号：US5822328A
公开(公告)日：1998-10-13
申请号：US647537
申请日：1996-05-15
申请人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
发明人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
IPC分类号： H04J3/06 , H04L7/04 , H04L7/10 , H04M11/06
CPC分类号： H04L7/046 , H04J3/0608 , H04M11/06 , H04L7/10
摘要： A time-division multiplexing synchronization mechanism employs a 1-bit/frame framing channel with a pattern that repeats every 2 frames. Acquisition and reacquisition of synchronization with such a framing pattern is enabled through the use of an explicit synchronization procedure. With this procedure, initial acquisition of frame synchronization as well as reframing after loss of synchronization are carried out while the transmission channel is carrying only a predefined bit pattern. When the receivers are in synchronization, synchronization is monitored and maintained using a 1-bit/frame framing channel, while the communications link is carrying multiplexed bit streams with the appropriate format.
摘要翻译：时分复用同步机制采用具有每2帧重复的模式的1比特/帧成帧信道。通过使用显式的同步过程，可以实现采集和重新获取与这种帧模式的同步。通过该过程，在传输信道仅承载预定义位模式的同时，执行帧同步的初始采集以及丢失同步之后的重构。当接收器处于同步状态时，使用1位/帧成帧通道来监视和维护同步，而通信链路则携带适当格式的多路复用位流。

6. 发明授权

US07454004B2 Method and system for verification of remote party identification 失效
标题翻译：远程方识别验证方法和系统
公开(公告)号：US07454004B2
公开(公告)日：2008-11-18
申请号：US10463633
申请日：2003-06-17
申请人： Uzi Shvadron
发明人： Uzi Shvadron
IPC分类号： H04M3/42
CPC分类号： G06Q20/02 , G06Q20/04 , G06Q20/425
摘要： A method for processing a transaction. The method includes receiving validation requests, automatically initiating one or more callbacks to an authorized transactor, and validating one or responses from the authorized transactor. The automatic initiation is in response to the validation requests, and according to pre-selected authorized transactor information. The responses from the authorized transactor are in reply to the callbacks. The validation is based upon the pre-selected authorized transactor information,
摘要翻译：一种处理交易的方法。该方法包括接收验证请求，自动发起对授权交易者的一个或多个回调，以及验证一个或来自授权交易者的响应。自动启动是响应验证请求，并根据预先选择的授权交易信息。来自授权交易者的回复正在回复回调。验证基于预先选择的授权交易者信息，

7. 发明授权

US5387910A Signal processor 失效
标题翻译：信号处理器
公开(公告)号：US5387910A
公开(公告)日：1995-02-07
申请号：US1481
申请日：1993-01-07
申请人： Yoav Medan , Uzi Shvadron
发明人： Yoav Medan , Uzi Shvadron
IPC分类号： G06F3/05 , G06F17/17 , G10L21/04 , H03H17/00 , H03H17/02 , H03H17/06 , H03M1/00 , H04B14/04 , H03M1/66
CPC分类号： H03H17/0642 , G06F17/17 , H03H17/0685
摘要： A signal processor is described for sampling rate conversion of a digitally sampled analog signal, the signal processor including an apparatus for generating an output sampled value for each output sampling instant, the output sampled value being equal to the input sampled value at the last input sampling instant if an input sampling instant has not occurred since the last output sampling instant and being calculated as an interpolation of input values at successive input sampling instants if an input sampling instant has occurred since the last output sampling instant. A virtual, analytic A/D-D/A conversion is employed using digital processing to convert from a given sampling rate to an arbitrary desired rate.
摘要翻译：描述信号处理器用于采样数字采样模拟信号的采样率转换，信号处理器包括用于为每个输出采样时刻产生输出采样值的装置，输出采样值等于最后输入采样时的输入采样值如果自上一个输出采样时刻以来没有发生输入采样时刻，并且如果自上次输出采样时刻以来已经发生输入采样时刻，则在连续输入采样时刻的输入值的内插计算即时。使用数字处理来使用虚拟的分析A / D-D / A转换，以从给定的采样率转换成任意所需的速率。

8. 发明授权

US5625845A System for facilitating continuous, real-time, unidirectional, and asynchronous intertask and end-device communication in a multimedia data processing system using open architecture data communication modules 失效
标题翻译：用于在使用开放架构数据通信模块的多媒体数据处理系统中促进连续，实时，单向和异步的任务和终端设备通信的系统
公开(公告)号：US5625845A
公开(公告)日：1997-04-29
申请号：US960976
申请日：1992-10-13
申请人： Gary G. Allran , Donald E. Carmon , Fetchi Chen , Jose A. Eduartez , Charles R. Knox , William W. Lawton , Llewellyn B. Marshall , Nathan A. Mitchell , Malcolm S. Ware , Raymond W. Weeks , Yoav Medan , Uzi Shvadron
发明人： Gary G. Allran , Donald E. Carmon , Fetchi Chen , Jose A. Eduartez , Charles R. Knox , William W. Lawton , Llewellyn B. Marshall , Nathan A. Mitchell , Malcolm S. Ware , Raymond W. Weeks , Yoav Medan , Uzi Shvadron
IPC分类号： H04L29/06 , H04L29/08 , G06F13/14 , G06F13/20
CPC分类号： H04L65/607 , H04L29/06 , H04L65/608 , H04L29/06027 , H04L69/32
摘要： A data processing system is provided for executing multimedia applications which interface with multimedia end devices that consume or produce at least one of (a) real-time and (b) asynchronous streamed data. The data processing system includes a central processing unit for data processing operations including execution of the multimedia application, a digital signal processor for processing data including the streamed data, and a plurality of modular components which cooperate to provide a substantially open architecture. The plurality of modular components include a plurality of modular multimedia software tasks which are executable by the digital signal processor and which may be called by the multimedia application for execution in the digital signal processor, as well as a plurality of data communication modules for linking selected ones of the plurality of modular multimedia software tasks with selected others of the plurality of modular multimedia software tasks, and for linking selected multimedia end devices with selected ones of the plurality of modular multimedia software tasks. Each of the plurality of data communication modules allows continuous, real-time and unidirectional communication of streamed data. The enhanced connectivity of the modular approach for the multimedia data processing system allows additional modular multimedia software tasks to be added to the plurality of modular multimedia software tasks and selectively linked to selected ones of the plurality of modular multimedia software tasks and selected ones of the multimedia end devices.
摘要翻译：提供了一种数据处理系统，用于执行与多媒体终端设备接口的多媒体应用程序，该多媒体终端设备消耗或产生（a）实时和（b）异步流数据中的至少一个。数据处理系统包括用于包括多媒体应用的执行的数据处理操作的中央处理单元，用于处理包括流传输的数据的数据的数字信号处理器，以及多个模块化组件，其协作以提供基本上开放的架构。多个模块化组件包括多个模块化多媒体软件任务，这些任务可由数字信号处理器执行，并且可由多媒体应用程序调用以在数字信号处理器中执行，以及多个用于链接所选择的数据通信模块所述多个模块化多媒体软件任务中的多个模块化多媒体软件任务中的一个与所选择的多个模块化多媒体软件任务中的其他任务相关联，并且用于将所选择的多媒体终端设备与多个模块化多媒体软件任务中的所选择的多个软多个数据通信模块中的每一个允许流式数据的连续的，实时的和单向的通信。用于多媒体数据处理系统的模块化方法的增强的连接性允许将附加的模块化多媒体软件任务添加到多个模块化多媒体软件任务中，并且选择性地链接到多个模块化多媒体软件任务中的选定模块多媒体软件任务和多媒体终端设备。

9. 发明授权

US08412722B2 Upload manager for use in a pattern matching accelerator 失效
标题翻译：上传管理器用于模式匹配加速器
公开(公告)号：US08412722B2
公开(公告)日：2013-04-02
申请号：US13022863
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Uzi Shvadron , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Uzi Shvadron , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

10. 发明申请

US20120203753A1 UPLOAD MANAGER FOR USE IN A PATTERN MATCHNG ACCELERATOR 失效
标题翻译：上传管理器用于模式匹配加速器
公开(公告)号：US20120203753A1
公开(公告)日：2012-08-09
申请号：US13022863
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Uzi Shvadron , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Uzi Shvadron , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

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