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1. 发明授权

US06915411B2 SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath 有权
标题翻译： SIMD处理器与矢量指针数据路径和向量计算数据通路同时运行
公开(公告)号：US06915411B2
公开(公告)日：2005-07-05
申请号：US10197733
申请日：2002-07-18
申请人： Jamie H. Moreno , Jeffrey Haskell Derby , Uzi Shvadron , Fredy Daniel Neeser , Victor Zyuban , Ayal Zaks , Shay Ben-David
发明人： Jamie H. Moreno , Jeffrey Haskell Derby , Uzi Shvadron , Fredy Daniel Neeser , Victor Zyuban , Ayal Zaks , Shay Ben-David
IPC分类号： G06F15/80
CPC分类号： G06F15/8092
摘要： A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.
摘要翻译：数字信号处理器（DSP）包括基于SIMD的组织，其中在多个单指令多数据（SIMD）数据通路或级联连接的级中执行操作。每个阶段的功能和数据值可以是不同的，包括每个阶段中不同的宽度（例如，每个值的不同位数）。通过向量指针数据路径中的向量指针寄存器间接地选择计算数据通路中的数据的操作数和目的地。每个向量指针寄存器包含多个指向计算数据路径的寄存器文件的指针。

2. 发明授权

US07017028B2 Apparatus and method for updating pointers for indirect and parallel register access 失效
标题翻译：用于更新用于间接和并行寄存器访问的指针的装置和方法
公开(公告)号：US07017028B2
公开(公告)日：2006-03-21
申请号：US10389212
申请日：2003-03-14
申请人： Shay Ben-David , Jeffrey Haskell Derby , Thomas W. Fox , Fredy Daniel Neeser , Jamie H. Moreno , Uzi Shvadron , Ayal Zaks
发明人： Shay Ben-David , Jeffrey Haskell Derby , Thomas W. Fox , Fredy Daniel Neeser , Jamie H. Moreno , Uzi Shvadron , Ayal Zaks
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G06F15/8084
摘要： An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.
摘要翻译：提供了一种用于更新用于访问多端口存储器中的一个或多个多个数据元素（即，一个或多个向量数据元素）的一个或多个多个指针（即一个或多个向量指针）的装置和方法。第一寄存器文件保存矢量指针，第二寄存器文件保存步幅数据，并且多个功能单元将来自第二寄存器堆的数据与来自第一寄存器堆的数据组合。将数据组合的结果传送到第一个寄存器文件并表示更新的向量指针。此外，提供第三寄存器文件用于保持模数选择器数据以指定用于循环寻址的循环缓冲器的大小。

3. 发明授权

US5822328A Frame synchronization mechanism for digital simultaneous voice/data modems 失效
标题翻译：数字同步语音/数据调制解调器的帧同步机制
公开(公告)号：US5822328A
公开(公告)日：1998-10-13
申请号：US647537
申请日：1996-05-15
申请人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
发明人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
IPC分类号： H04J3/06 , H04L7/04 , H04L7/10 , H04M11/06
CPC分类号： H04L7/046 , H04J3/0608 , H04M11/06 , H04L7/10
摘要： A time-division multiplexing synchronization mechanism employs a 1-bit/frame framing channel with a pattern that repeats every 2 frames. Acquisition and reacquisition of synchronization with such a framing pattern is enabled through the use of an explicit synchronization procedure. With this procedure, initial acquisition of frame synchronization as well as reframing after loss of synchronization are carried out while the transmission channel is carrying only a predefined bit pattern. When the receivers are in synchronization, synchronization is monitored and maintained using a 1-bit/frame framing channel, while the communications link is carrying multiplexed bit streams with the appropriate format.
摘要翻译：时分复用同步机制采用具有每2帧重复的模式的1比特/帧成帧信道。通过使用显式的同步过程，可以实现采集和重新获取与这种帧模式的同步。通过该过程，在传输信道仅承载预定义位模式的同时，执行帧同步的初始采集以及丢失同步之后的重构。当接收器处于同步状态时，使用1位/帧成帧通道来监视和维护同步，而通信链路则携带适当格式的多路复用位流。

4. 发明授权

US10534608B2 Local computation logic embedded in a register file to accelerate programs 有权
公开(公告)号：US10534608B2
公开(公告)日：2020-01-14
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/78 , G06F15/16 , G06F9/30 , G06F9/38
摘要： A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

5. 发明授权

US06889346B2 Scoping of real time signals of remote communication systems over a computer network: systems, methods and program products 失效
标题翻译：通过计算机网络实现远程通信系统的实时信号范围：系统，方法和程序产品
公开(公告)号：US06889346B2
公开(公告)日：2005-05-03
申请号：US09906371
申请日：2001-07-16
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F11/00 , G06F13/00
CPC分类号： H04L47/76 , H04L41/0896 , H04L43/50 , H04L63/083
摘要： A remote controller is coupled to a target system via a computer network A real time probe is installed in software executing on a target system, typically a Digital Signal Processor (DSP). The remote controller includes a “debugger user interface” which accepts and interprets scoping commands issued by a developer. A controller network driver constructs appropriate network packets to be sent over the network to the target system. The target system has a control processor which runs a target network driver for receiving the network packets containing the scoping commands. The scoping commands are sent to an “embedded debugger” which performs the requested probing/scoping. When the DSP code runs across an address where the probe is installed, the embedded debugger will collect the signal values. The collected scope data will be interleaved and sent to the target network driver which, will encapsulate the information into suitable packets to send back to the controller via the network.
摘要翻译：遥控器经由计算机网络耦合到目标系统。实时探测器安装在目标系统（通常为数字信号处理器（DSP））上执行的软件中。遥控器包括一个“调试器用户界面”，它接受并解释开发人员发出的作用域命令。控制器网络驱动程序构建要通过网络发送到目标系统的适当网络数据包。目标系统具有控制处理器，该控制处理器运行目标网络驱动器以接收包含范围命令的网络分组。范围指令被发送到执行所请求的探测/范围的“嵌入式调试器”。当DSP代码在安装探头的地址上运行时，嵌入式调试器将收集信号值。收集的范围数据将被交织并发送到目标网络驱动程序，目标网络驱动程序将将信息封装到适当的数据包中，以通过网络发送回控制器。

6. 发明申请

US20130152099A1 DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES 有权
公开(公告)号：US20130152099A1
公开(公告)日：2013-06-13
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

7. 发明授权

US08200905B2 Effective prefetching with multiple processors and threads 失效
标题翻译：有效的预取与多个处理器和线程
公开(公告)号：US08200905B2
公开(公告)日：2012-06-12
申请号：US12192072
申请日：2008-08-14
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

8. 发明授权

US07325122B2 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US07325122B2
公开(公告)日：2008-01-29
申请号：US10783757
申请日：2004-02-20
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F13/16 , G06F15/163
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

9. 发明授权

US07003030B2 Receivers, methods, and computer program products for an analog modem that receives data signals from a digital modem 失效
标题翻译：用于从数字调制解调器接收数据信号的模拟调制解调器的接收器，方法和计算机程序产品
公开(公告)号：US07003030B2
公开(公告)日：2006-02-21
申请号：US10635194
申请日：2003-08-06
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Robert F. H. Fischer , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Robert F. H. Fischer , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
IPC分类号： H03K5/159
CPC分类号： H04L7/0062 , H04L7/0029 , H04L2025/03363 , H04L2025/0342 , H04L2025/0349
摘要： Receivers, methods, and computer program products can be used to demodulate a data signal transmitted from a digital source, which has a network sampling rate that is synchronized with a network clock. In an illustrative embodiment, a receiver includes a two-stage interpolator that receives digital samples of the data signal as an input and produces an interpolated digital sample stream to be filtered by an adaptive fractionally spaced decision feedback equalizer. The digital samples received in the interpolator are synchronized with a local clock; however, the interpolated sample stream is synchronized with the network clock. A slicer generates symbols for the samples output from the decision feedback equalizer by comparing the samples with a reference signaling alphabet. The receiver can be used in a V.90 client modem to demodulate pulse code modulated (PCM) data transmitted as pulse amplitude modulated (PAM) signals from a digital network. In addition, the receiver is compatible with legacy analog modem front ends and transmitters. The two-stage interpolator allows the timing synchronization to be performed with extremely fine granularity, which can be useful in PCM modems that typically require relatively high signal to noise ratios.
摘要翻译：接收器，方法和计算机程序产品可用于解调从具有与网络时钟同步的网络采样速率的数字源发送的数据信号。在说明性实施例中，接收机包括二阶插值器，其接收作为输入的数据信号的数字样本，并产生经过自适应分数间隔的判决反馈均衡器滤波的内插数字样本流。在内插器中接收的数字样本与本地时钟同步; 然而，插值的采样流与网络时钟同步。切片器通过将样本与参考信号字母表进行比较来生成从判决反馈均衡器输出的样本的符号。接收机可用于V.90客户端调制解调器中，以解调从数字网络传输的脉冲编码调制（PCM）数据作为脉冲幅度调制（PAM）信号。此外，接收机与传统模拟调制解调器前端和发射机兼容。两级内插器允许以非常精细的粒度执行定时同步，这在通常需要相对较高的信噪比的PCM调制解调器中是有用的。

10. 发明授权

US06940864B2 Network access traffic sorter 失效
标题翻译：网络访问流量分拣机
公开(公告)号：US06940864B2
公开(公告)日：2005-09-06
申请号：US09906352
申请日：2001-07-16
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
IPC分类号： H04L12/56 , H04L29/06 , H04Q12/28
CPC分类号： H04L65/605 , H04L29/06027 , H04L47/2441 , H04L47/2458 , H04L47/365 , H04L47/50 , H04L65/80 , H04L69/22
摘要： Packetized voice, video, and data traffic (data frames) are received in a communication traffic sorter. The data frames have a dispatch priority corresponding to their transmission characteristics (flow) and a quality of service parameters. The communication traffic sorter analyzes information in data packets within each data frame and determines an optimum flow for the data frames. A data frame is assigned to a selected queue based on an analysis of the information in its data packets. A data frame may also be assigned to a queue based on a prior analysis of a data frame with like transmission characteristics. Results of analysis are stored and indexed to facilitate processing of subsequent data frames. The network access sorter has circuits to un-pack and re-pack the data frame, when called for, to allow user transmitted data to be processed to create a modified data frame. The data frame may then be dispatched with a second dispatch priority on a bus for distribution to end users where previously assigned quality of service is maintained or exceeded.
摘要翻译：分组化语音，视频和数据业务（数据帧）在通信流量分类器中被接收。数据帧具有对应于其传输特性（流）和服务质量参数的调度优先级。通信流量分类器分析每个数据帧内的数据分组中的信息，并确定数据帧的最佳流。基于对其数据分组中的信息的分析，将数据帧分配给所选择的队列。基于具有相似传输特性的数据帧的先前分析，也可以将数据帧分配给队列。分析结果存储和索引，以便于后续数据帧的处理。网络访问分拣机具有用于在被要求时解除数据帧的打包和重新打包的电路，以允许用户传送的数据被处理以创建经修改的数据帧。然后可以在总线上以第二调度优先级调度数据帧，以便分发给维护或超过先前分配的服务质量的最终用户。

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