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1. 发明授权

US08200905B2 Effective prefetching with multiple processors and threads 失效
标题翻译：有效的预取与多个处理器和线程
公开(公告)号：US08200905B2
公开(公告)日：2012-06-12
申请号：US12192072
申请日：2008-08-14
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

2. 发明申请

US20120246406A1 EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS 失效
标题翻译：有效的预处理与多个处理器和螺纹
公开(公告)号：US20120246406A1
公开(公告)日：2012-09-27
申请号：US13488215
申请日：2012-06-04
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

3. 发明授权

US07519793B2 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US07519793B2
公开(公告)日：2009-04-14
申请号：US11944028
申请日：2007-11-21
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F13/16 , G06F15/163
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

4. 发明授权

US07352802B2 System and method for controlling line driver power in digital subscriber line modems 有权
标题翻译：用于数字用户线路调制解调器控制线路驱动器功率的系统和方法
公开(公告)号：US07352802B2
公开(公告)日：2008-04-01
申请号：US11237001
申请日：2005-09-28
申请人： Gordon Taylor Davis , Jeffrey Haskell Derby , Evangelos Stavros Eleftheriou , Sedat Oelcer , Malcolm Scott Ware
发明人： Gordon Taylor Davis , Jeffrey Haskell Derby , Evangelos Stavros Eleftheriou , Sedat Oelcer , Malcolm Scott Ware
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/028 , H04L27/2626 , H04M11/062 , Y02D50/44
摘要： A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flaw of data packets to the DSLs.
摘要翻译：适用于集成DSLAM服务器线路卡的低功率DSL调制解调器发射机在数据可用于传输和仅具有控制信道或控制信道的物理帧的情况下传输包括控制信道和数据字段的全功率物理帧，当数据不可用于传输时的低功率同步字段。以及一种通过选择性地将数据分组的缺陷限制到DSL来控制集成DSLAM中消耗的总功率的方法。

5. 发明授权

US07272663B2 Method and system for delineating data segments subjected to data compression 有权
标题翻译：描述受数据压缩的数据段的方法和系统
公开(公告)号：US07272663B2
公开(公告)日：2007-09-18
申请号：US09941043
申请日：2001-08-28
申请人： Gordon Taylor Davis , Jeffrey Haskell Derby , Malcolm Scott Ware
发明人： Gordon Taylor Davis , Jeffrey Haskell Derby , Malcolm Scott Ware
IPC分类号： G06F15/16
CPC分类号： H04L12/5601
摘要： A method and system for compressing and transmitting data using asynchronous transfer mode (ATM) is disclosed. The data include a plurality of segments. Each of the plurality of segments has a first end and a second end. In one aspect, the method and system include representing the first end of a segment with a partition compression code word and compressing a remaining portion of the segment. The method and system could also combine the marking of the boundary and subsequent data into a compound compression code word. In another aspect, the method and system include representing the first end of a segment with a transparent mode command, transmitting the transparent mode command, and transmitting a remaining portion of the segment.
摘要翻译：公开了一种使用异步传输模式（ATM）压缩和传输数据的方法和系统。数据包括多个段。多个段中的每一个具有第一端和第二端。在一个方面，所述方法和系统包括用分区压缩码字表示段的第一端并压缩段的剩余部分。该方法和系统还可以将边界的标记和后续数据组合成复合压缩码字。在另一方面，所述方法和系统包括用透明模式命令表示段的第一端，发送透明模式命令和发送段的剩余部分。

6. 发明授权

US06826157B1 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR CONTROLLING DATA RATE REDUCTIONS IN A COMMUNICATION DEVICE BY USING A PLURALITY OF FILTERS TO DETECT SHORT-TERM BURSTS OF ERRORS AND LONG-TERM SUSTAINABLE ERRORS 失效
标题翻译：系统，方法和计算机程序产品，用于通过使用多个滤波器来检测短期错误和长期可持续错误来控制通信设备中的数据速率减少
公开(公告)号：US06826157B1
公开(公告)日：2004-11-30
申请号：US09431972
申请日：1999-10-29
申请人： Gordon Taylor Davis , Jeffrey Haskell Derby , Malcolm Scott Ware , Charles Robert Young
发明人： Gordon Taylor Davis , Jeffrey Haskell Derby , Malcolm Scott Ware , Charles Robert Young
IPC分类号： H04J116
CPC分类号： H04L1/0002
摘要： Data rate control systems, methods, and computer program products in which an error counter is maintained that contains an error count. The error counter is periodically sampled to determine a sampling interval error count corresponding to a change in the error count since a previous read of the error counter. The sampling interval error count is provided to a first filter that is characterized by a slow time-constant and a second filter that is characterized by a fast time-constant. The first filter generates a slow-filtered sampling interval error count while the second filter generates a fast-filtered sampling interval error count, which are used as a basis for generating a data rate slowdown request signal. More specifically, the data rate slowdown request signal is generated if either the slow-filtered sampling interval error count or the fast-filtered sampling interval error count exceeds a threshold respectively associated therewith. Advantageously, the first filter, which is characterized by a slow time-constant, may be used to respond to lower numbers of errors that are sustained over an extended time period while the second filter, which is characterized by a fast time-constant, may be used to respond to large error bursts spanning a shorter time period. Moreover, by filtering the errors accumulated during each sampling interval, sensitivity with respect to the position in time of a given error burst relative to boundaries between sampling intervals may be avoided.
摘要翻译：数据速率控制系统，方法和计算机程序产品，其中维护包含错误计数的错误计数器。周期性地对误差计数器进行采样，以确定与错误计数器的先前读取相对应的误差计数变化的采样间隔误差计数。采样间隔误差计数被提供给以慢时间常数为特征的第一滤波器和以快速时间常数为特征的第二滤波器。第一个滤波器产生慢速滤波的采样间隔误差计数，而第二个滤波器产生快速滤波的采样间隔误差计数，用于产生数据速率减速请求信号的基础。更具体地，如果缓慢滤波的采样间隔误差计数或快速滤波的采样间隔误差计数超过分别与其相关联的阈值，则产生数据速率减速请求信号。有利地，以慢时间常数为特征的第一滤波器可用于响应在较长时间段内持续的较低数量的误差，而以快速时间常数为特征的第二滤波器可以用于响应跨越较短时间段的大错误突发。此外，通过对在每个采样间隔期间累积的误差进行滤波，可以避免相对于采样间隔之间的边界相对于给定误差突发的时间位置的灵敏度。

7. 发明授权

US06665336B2 MODEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR SELECTING AN OPTIMUM DATA RATE USING ERROR SIGNALS REPRESENTING THE DIFFERENCE BETWEEN THE OUTPUT OF AN EQUALIZER AND THE OUTPUT OF A SLICER OR DETECTOR 失效
标题翻译：使用错误信号选择最佳数据速率的方式，方法和计算机程序产品，表示均衡器的输出与切换器或检测器的输出之间的差异
公开(公告)号：US06665336B2
公开(公告)日：2003-12-16
申请号：US10428357
申请日：2003-05-02
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
IPC分类号： H04B1700
CPC分类号： H04L1/0021 , H04L1/0002 , H04L25/03057 , H04L25/4927 , H04L2025/03388 , Y02D50/10
摘要： Modems, methods, and computer program products select a data rate based on error signals in a modem. In an illustrative embodiment, error signals representing the difference between an output of an equalizer and an output of a detector are accumulated and an average error value is computed therefrom. A signal to noise ratio is determined using the average error value. The signal to noise ratio is then used to select a data rate. In another illustrative embodiment, the mean squared error at the output of the equalizer is determined and then used, along with the probability of error in correctly detecting a symbol, to select a data rate. Incorrect decisions in detecting received data symbols can cause a catastrophic failure in a decision feedback equalizer used in a modem receiver as errors are repeatedly fed back causing the tap coefficients for the equalizer filters to be shifted from their normal operating values. By adjusting the data rate in accordance with the error signals generated in a modem receiver, the decision feedback equalizer can operate with greater stability as the data rate can be reduced in response to increased noise conditions.
摘要翻译：调制解调器，方法和计算机程序产品根据调制解调器中的错误信号选择数据速率。在说明性实施例中，代表均衡器的输出和检测器的输出之间的差的误差信号被累加，并且从其计算出平均误差值。使用平均误差值确定信噪比。然后使用信噪比来选择数据速率。在另一说明性实施例中，确定均衡器的输出处的均方误差，然后与正确检测符号的误差概率一起使用以选择数据速率。检测接收到的数据符号时的不正确决定可能导致在调制解调器接收机中使用的判决反馈均衡器中的灾难性故障，因为错误被反复反馈，导致均衡器滤波器的抽头系数从其正常操作值偏移。通过根据在调制解调器接收机中产生的误差信号来调整数据速率，当响应于增加的噪声条件可以减小数据速率时，判决反馈均衡器可以更稳定地工作。

8. 发明授权

US06341360B1 Decision feedback equalizers, methods, and computer program products for detecting severe error events and preserving equalizer filter characteristics in response thereto 失效
标题翻译：用于检测严重错误事件的决策反馈均衡器，方法和计算机程序产品，并且响应于此而保持均衡器滤波器特性
公开(公告)号：US06341360B1
公开(公告)日：2002-01-22
申请号：US09264094
申请日：1999-03-08
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Ajay Dholakia , Evangelos Stavros Eleftheriou , Dongming Hwang , Fredy D. Neeser , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F1100
CPC分类号： H04L25/4927 , H04L25/03057 , H04L2025/03363 , H04L2025/03694
摘要： Decision feedback equalizers having a stabilization capability, and methods and computer program products for stabilizing a decision feedback equalizer under severe error conditions use output samples from an equalizer to determine whether a severe error event has occurred in accordance with predefined criteria. If a severe error occurs, then a determination is made to evaluate whether the number of severe errors that have occurred has exceeded a threshold. If the threshold has been exceeded, then the coefficients for the filter(s) in the decision feedback equalizer are preserved in their current state. Severe errors can cause the equalizer filter coefficients to be pulled away from their normal operating values, which can result in several modulation cycles passing before the coefficients are restored. By preserving the equalizer filter coefficients under severe error conditions, the present invention prevents sharp or dramatic changes to the coefficient values from their steady state values allowing the decision feedback equalizer to recover more quickly from the errors.
摘要翻译：具有稳定能力的判决反馈均衡器，以及用于在严重误差条件下稳定判决反馈均衡器的方法和计算机程序产品，使用来自均衡器的输出样本来确定是否根据预定标准发生严重错误事件。如果发生严重的错误，则进行判断，以评估发生的严重错误的数量是否超过阈值。如果超过阈值，则判决反馈均衡器中滤波器的系数保持在其当前状态。严重的错误可能导致均衡器滤波器系数从其正常工作值被拉开，这可能导致在系数恢复之前通过的多个调制周期。通过在严重的误差条件下保持均衡器滤波器系数，本发明防止系数值从其稳定状态值的急剧或显着变化，从而允许判决反馈均衡器从错误中更快地恢复。

9. 发明授权

US06889346B2 Scoping of real time signals of remote communication systems over a computer network: systems, methods and program products 失效
标题翻译：通过计算机网络实现远程通信系统的实时信号范围：系统，方法和程序产品
公开(公告)号：US06889346B2
公开(公告)日：2005-05-03
申请号：US09906371
申请日：2001-07-16
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F11/00 , G06F13/00
CPC分类号： H04L47/76 , H04L41/0896 , H04L43/50 , H04L63/083
摘要： A remote controller is coupled to a target system via a computer network A real time probe is installed in software executing on a target system, typically a Digital Signal Processor (DSP). The remote controller includes a “debugger user interface” which accepts and interprets scoping commands issued by a developer. A controller network driver constructs appropriate network packets to be sent over the network to the target system. The target system has a control processor which runs a target network driver for receiving the network packets containing the scoping commands. The scoping commands are sent to an “embedded debugger” which performs the requested probing/scoping. When the DSP code runs across an address where the probe is installed, the embedded debugger will collect the signal values. The collected scope data will be interleaved and sent to the target network driver which, will encapsulate the information into suitable packets to send back to the controller via the network.
摘要翻译：遥控器经由计算机网络耦合到目标系统。实时探测器安装在目标系统（通常为数字信号处理器（DSP））上执行的软件中。遥控器包括一个“调试器用户界面”，它接受并解释开发人员发出的作用域命令。控制器网络驱动程序构建要通过网络发送到目标系统的适当网络数据包。目标系统具有控制处理器，该控制处理器运行目标网络驱动器以接收包含范围命令的网络分组。范围指令被发送到执行所请求的探测/范围的“嵌入式调试器”。当DSP代码在安装探头的地址上运行时，嵌入式调试器将收集信号值。收集的范围数据将被交织并发送到目标网络驱动程序，目标网络驱动程序将将信息封装到适当的数据包中，以通过网络发送回控制器。

10. 发明授权

US07072344B2 Redistribution of excess bandwidth in networks for optimized performance of voice and data sessions: methods, systems and program products 失效
标题翻译：在网络中重新分配超额带宽，以优化语音和数据会话的性能：方法，系统和程序产品
公开(公告)号：US07072344B2
公开(公告)日：2006-07-04
申请号：US09906485
申请日：2001-07-16
申请人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon Taylor Davis , Jeffrey Haskell Derby , Dongming Hwang , Clark Debs Jeffries , Malcolm Scott Ware , Hua Ye
IPC分类号： H04L12/56
CPC分类号： H04L65/80 , H04L29/06027 , H04L47/70 , H04L47/745 , H04L47/748 , H04L47/765 , H04L47/801
摘要： A packet network redistributes excess bandwidth for voice and data sessions applying a Quality of Service (QoS) algorithm. The network includes interacting client stations using H.323 protocol managing bit rate according to an algorithm as voice and data sessions are added or removed from the network. The client stations include codecs coupled to the network. The codecs provide voice sessions at a minimum bandwidth using a voice codec bit rate and preferred bandwidth using another voice codec bit rate. A first algorithm applies the QoS algorithm allocating bandwidth between interacting client stations after the addition of a new voice or data session when there is insufficient bandwidth for the new session to receive preferred bandwidth. A second algorithm is applied when a voice or data session is removed from the interacting client stations. If any session is allocated minimum bandwidth the QoS increases a voice session at minimum bandwidth to preferred bandwidth if excess bandwidth is available.
摘要翻译：分组网络重新分配应用服务质量（QoS）算法的语音和数据会话的多余带宽。该网络包括使用H.323协议的交互式客户端站，根据算法管理比特率，因为语音和数据会话被从网络添加或删除。客户端站包括耦合到网络的编解码器。编解码器使用语音编解码器比特率和使用另一语音编解码器比特率的优选带宽以最小带宽提供语音会话。第一种算法在增加新的语音或数据会话之后，在新会话接收到优先带宽的带宽不足的情况下，应用QoS算法在交互的客户端站之间分配带宽。当从交互的客户端站移除语音或数据会话时，应用第二种算法。如果任何会话被分配最小带宽，则QoS会将最小带宽的语音会话增加到优先带宽，如果有超额带宽可用。

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