专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090309143A1 PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE 有权
公开(公告)号：US20090309143A1
公开(公告)日：2009-12-17
申请号：US12139524
申请日：2008-06-16
申请人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
发明人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14612
摘要： A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.

2. 发明授权

US07923750B2 Pixel sensor cell, methods and design structure including optically transparent gate 有权
标题翻译：像素传感器单元，方法和设计结构包括光学透明门
公开(公告)号：US07923750B2
公开(公告)日：2011-04-12
申请号：US12139524
申请日：2008-06-16
申请人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
发明人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
IPC分类号： H01L31/062 , H01L31/113 , H01L31/00 , H01L29/74 , H01L31/111
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14612
摘要： A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.
摘要翻译：像素传感器单元，用于制造或操作像素传感器单元的方法和用于制造像素传感器单元的设计结构各自包括半导体衬底，其包括通过沟道区域与浮动扩散区域分离的光活性区域。至少一个栅极介质至少部分地位于半导体衬底之间，介于光活性区域和浮动扩散区域之间，并且至少一个光学透明栅极位于栅极电介质上并且至少部分地位于沟道区域上。优选地，至少一个栅极电介质也位于光活性区域之上，并且至少一个光学透明栅极也至少部分地位于光活性区域上，以在像素传感器单元内提供增强的电荷转移能力，其是通常是CMOS像素传感器单元。

3. 发明申请

US20090311822A1 PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE 审中-公开
标题翻译：像素传感器单元，包括光学透明门的方法和设计结构
公开(公告)号：US20090311822A1
公开(公告)日：2009-12-17
申请号：US12139523
申请日：2008-06-16
申请人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
发明人： James William Adkisson , Rajendran Krishnasamy , John Joseph Ellis-Monaghan , Solomon Mulugeta , Charles Francis Musante , Richard J. Rassel
IPC分类号： H01L21/00
CPC分类号： H01L27/14614 , H01L27/14643 , H01L27/14689
摘要： A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.
摘要翻译：像素传感器单元，用于制造或操作像素传感器单元的方法和用于制造像素传感器单元的设计结构各自包括半导体衬底，其包括通过沟道区域与浮动扩散区域分离的光活性区域。至少一个栅极介质至少部分地位于半导体衬底之间，介于光活性区域和浮动扩散区域之间，并且至少一个光学透明栅极位于栅极电介质上并且至少部分地位于沟道区域上。优选地，至少一个栅极电介质也位于光活性区域之上，并且至少一个光学透明栅极也至少部分地位于光活性区域上，以在像素传感器单元内提供增强的电荷转移能力，其是通常是CMOS像素传感器单元。

4. 发明授权

US08138531B2 Structures, design structures and methods of fabricating global shutter pixel sensor cells 有权
标题翻译：制造全局快门像素传感器单元的结构，设计结构和方法
公开(公告)号：US08138531B2
公开(公告)日：2012-03-20
申请号：US12561581
申请日：2009-09-17
申请人： James William Adkisson , John Joseph Ellis-Monaghan , Mark David Jaffe , Richard John Rassel
发明人： James William Adkisson , John Joseph Ellis-Monaghan , Mark David Jaffe , Richard John Rassel
IPC分类号： H01L31/113
CPC分类号： H01L27/14609 , H01L27/1461 , H01L27/1463 , H01L27/14643 , H01L27/14689
摘要： Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.
摘要翻译：像素传感器单元，制造像素传感器单元的方法和像素传感器单元的设计结构。所述像素传感器单元包括：在半导体层的第一区域中的光电二极管主体; 半导体层的第二区域中的浮动扩散节点，位于第一和第二区域之间并邻接第一和第二区域的半导体层的第三区域; 以及在所述半导体层中的绝缘隔离，围绕所述第一，第二和第三区域的介电隔离，所述介质隔离邻接所述第一，第二和第三区域以及所述光电二极管主体，所述介电隔离件不邻接所述浮动扩散节点，所述第二介于介电隔离和浮动扩散节点之间的区域。

5. 发明申请

US20110062542A1 STRUCTURES, DESIGN STRUCTURES AND METHODS OF FABRICATING GLOBAL SHUTTER PIXEL SENSOR CELLS 有权
标题翻译：制作全球快门像素传感器细胞的结构，设计结构和方法
公开(公告)号：US20110062542A1
公开(公告)日：2011-03-17
申请号：US12561581
申请日：2009-09-17
申请人： James William Adkisson , John Joseph Ellis-Monaghan , Mark David Jaffe , Richard John Rassel
发明人： James William Adkisson , John Joseph Ellis-Monaghan , Mark David Jaffe , Richard John Rassel
IPC分类号： H01L31/12 , H01L31/18 , G06F17/50
CPC分类号： H01L27/14609 , H01L27/1461 , H01L27/1463 , H01L27/14643 , H01L27/14689
摘要： Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.
摘要翻译：像素传感器单元，制造像素传感器单元的方法和像素传感器单元的设计结构。所述像素传感器单元包括：在半导体层的第一区域中的光电二极管主体; 半导体层的第二区域中的浮动扩散节点，位于第一和第二区域之间并邻接第一和第二区域的半导体层的第三区域; 以及在所述半导体层中的绝缘隔离，围绕所述第一，第二和第三区域的介电隔离，所述介质隔离邻接所述第一，第二和第三区域以及所述光电二极管主体，所述介电隔离件不邻接所述浮动扩散节点，所述第二介于介电隔离和浮动扩散节点之间的区域。

6. 发明授权

US06326260B1 Gate prespacers for high density, high performance DRAMs 失效
标题翻译：用于高密度，高性能DRAM的Gate Prepacers
公开(公告)号：US06326260B1
公开(公告)日：2001-12-04
申请号：US09599703
申请日：2000-06-22
申请人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
发明人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823462 , H01L27/10873
摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
摘要翻译：提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及所述多晶硅层在所述导体材料层上形成氮化物覆盖层形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

7. 发明授权

US08647913B2 Image sensor, method and design structure including non-planar reflector 失效
标题翻译：图像传感器，方法和设计结构包括非平面反射器
公开(公告)号：US08647913B2
公开(公告)日：2014-02-11
申请号：US13614210
申请日：2012-09-13
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L27/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

8. 发明授权

US07790559B2 Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes 失效
标题翻译：具有高K栅极电介质层和金属栅电极的半导体晶体管
公开(公告)号：US07790559B2
公开(公告)日：2010-09-07
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

9. 发明授权

US08227874B2 Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes 有权
标题翻译：具有高K栅极电介质层和金属栅电极的半导体晶体管
公开(公告)号：US08227874B2
公开(公告)日：2012-07-24
申请号：US12861913
申请日：2010-08-24
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

10. 发明申请

US20090212376A1 SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES 失效
标题翻译：具有高K栅电介质层和金属栅极电极的半导体晶体管
公开(公告)号：US20090212376A1
公开(公告)日：2009-08-27
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式