专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08698312B2 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging 有权
标题翻译：包括用于在包装期间和之后增强机械强度的混合金属化层堆叠的半导体器件
公开(公告)号：US08698312B2
公开(公告)日：2014-04-15
申请号：US11046986
申请日：2005-01-31
申请人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
发明人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
IPC分类号： H01L23/48
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.
摘要翻译：将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

2. 发明申请

US20050242435A1 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging 有权
标题翻译：包括用于在包装期间和之后增强机械强度的混合金属化层堆叠的半导体器件
公开(公告)号：US20050242435A1
公开(公告)日：2005-11-03
申请号：US11046986
申请日：2005-01-31
申请人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
发明人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
IPC分类号： H01L21/4763 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/50 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.
摘要翻译：将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

3. 发明授权

US07671362B2 Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing 失效
标题翻译：用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
公开(公告)号：US07671362B2
公开(公告)日：2010-03-02
申请号：US11953568
申请日：2007-12-10
申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
发明人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
IPC分类号： H01L23/58
CPC分类号： H01L22/12 , H01L22/34
摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
摘要翻译：集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化，相同的沉积工艺条件。

4. 发明申请

US20070004214A1 TECHNIQUE FOR REDUCING ETCH DAMAGE DURING THE FORMATION OF VIAS AND TRENCHES IN INTERLAYER DIELECTRICS 失效
标题翻译：在中间层电介质中形成VIAS和TRENCHES时减少蚀刻损伤的技术
公开(公告)号：US20070004214A1
公开(公告)日：2007-01-04
申请号：US11380094
申请日：2006-04-25
申请人： Matthias Schaller , Massud Aminpur , James Werking
发明人： Matthias Schaller , Massud Aminpur , James Werking
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.
摘要翻译：通过执行用于在具有不同去除速率的金属化层中形成通孔开口和描绘沟槽或开口区域的第一常用蚀刻工艺，可以延迟描绘沟槽或开放区域中的蚀刻前沿，从而显着降低晶片电弧的可能性。随后，在另一常见的蚀刻工艺中，描绘沟槽或开放区域可以被蚀刻到相应的蚀刻停止层，在此期间在通孔开口上方形成沟槽。

5. 发明申请

US20090146143A1 TEST STRUCTURE FOR DETERMINING OPTIMAL SEED AND LINER LAYER THICKNESSES FOR DUAL DAMASCENE PROCESSING 失效
标题翻译：用于确定双重加工过程的最佳种子和层间厚度的测试结构
公开(公告)号：US20090146143A1
公开(公告)日：2009-06-11
申请号：US11953568
申请日：2007-12-10
申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
发明人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
IPC分类号： H01L23/58 , H01L21/4763
CPC分类号： H01L22/12 , H01L22/34
摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
摘要翻译：集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化，相同的沉积工艺条件。

6. 发明申请

US20090098728A1 STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME 审中-公开
标题翻译：使用双BELAYER处理方案的互连结构CU LINER
公开(公告)号：US20090098728A1
公开(公告)日：2009-04-16
申请号：US11870649
申请日：2007-10-11
申请人： Stephan Grunow , Thomas McCarroll Shaw , Andrew H. Simon , Chih-Chao Yang , Tiblor Bolom , James Werking
发明人： Stephan Grunow , Thomas McCarroll Shaw , Andrew H. Simon , Chih-Chao Yang , Tiblor Bolom , James Werking
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76805 , H01L21/76865
摘要： The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN and Ta liners into the first metallization layer. After sputter etching, the method then lines the via opening with second TaN and Ta liners. Next, the method deposits a conductor into the via opening, thereby connecting the first and second metallization layers.
摘要翻译：所公开的方法通过图案化覆盖在第一金属化层上的绝缘体层以包括通孔开口在半导体结构中的金属化层之间形成通孔。该方法用TaN和Ta衬垫将通孔开口排列，然后通过TaN和Ta衬垫将通孔开口溅射到第一金属化层中。在溅射蚀刻之后，该方法然后将通孔与第二TaN和Ta衬垫分开。接下来，该方法将导体沉积到通孔开口中，从而连接第一和第二金属化层。

7. 发明授权

US07465639B1 Method for fabricating an SOI device 有权
标题翻译： SOI器件的制造方法
公开(公告)号：US07465639B1
公开(公告)日：2008-12-16
申请号：US11133969
申请日：2005-05-20
申请人： Mario M. Pelella , Richard K. Klein , James Werking
发明人： Mario M. Pelella , Richard K. Klein , James Werking
IPC分类号： H01L21/20
CPC分类号： H01L21/84
摘要： A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.
摘要翻译：提供了一种用于制造绝缘体上硅（SOI）器件的方法，该器件包括硅衬底，覆盖硅衬底的掩埋绝缘体层和覆盖在掩埋绝缘体层上的单晶硅层。该方法包括以下步骤：形成耦合在第一电压总线和第二电压总线之间的MOS电容器。 MOS电容器具有形成MOS电容器的第一板的栅电极材料和形成MOS电容器的第二板的栅极电极材料下面的单晶硅层中的杂质掺杂区域。第一电压总线耦合到电容器的第一板，第二电压总线耦合到电容器的第二板。该方法还包括形成将MOS电容器的第二板耦合到硅衬底的放电路径。

8. 发明授权

US07309654B2 Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics 失效
标题翻译：用于在层间电介质形成通孔和沟槽期间减少蚀刻损伤的技术
公开(公告)号：US07309654B2
公开(公告)日：2007-12-18
申请号：US11380094
申请日：2006-04-25
申请人： Matthias Schaller , Massud Aminpur , James Werking
发明人： Matthias Schaller , Massud Aminpur , James Werking
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.
摘要翻译：通过执行用于在具有不同去除速率的金属化层中形成通孔开口和描绘沟槽或开口区域的第一常用蚀刻工艺，可以延迟描绘沟槽或开放区域中的蚀刻前沿，从而显着降低晶片电弧的可能性。随后，在另一常见的蚀刻工艺中，描绘沟槽或开放区域可以被蚀刻到相应的蚀刻停止层，在此期间在通孔开口上方形成沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式