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1. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

2. 发明授权

US06610594B2 Locally increasing sidewall density by ion implantation 有权
公开(公告)号：US06610594B2
公开(公告)日：2003-08-26
申请号：US09902024
申请日：2001-07-10
申请人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
发明人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76802 , H01L21/7681 , H01L21/76828 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

3. 发明授权

US06268255B1 Method of forming a semiconductor device with metal silicide regions 有权
标题翻译：用金属硅化物区形成半导体器件的方法
公开(公告)号：US06268255B1
公开(公告)日：2001-07-31
申请号：US09479402
申请日：2000-01-06
申请人： Paul R. Besser , Christian Zistl , Nicholas J. Kepler
发明人： Paul R. Besser , Christian Zistl , Nicholas J. Kepler
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/6659
摘要： The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.
摘要翻译：本发明涉及制造半导体器件的方法。在一个说明性实施例中，该方法包括形成由多晶硅组成的第一层，在多晶硅层上形成由难熔金属组成的第二层，并将第二层的至少一部分转化为第一金属硅化物。该方法还包括在难熔金属层或第一金属硅化物层之上形成抗反射涂层，以及对第一金属硅化物层和多晶硅层进行构图以限定由第一金属硅化物区和多晶硅层，在衬底中形成多个源极/漏极区域，在至少栅极堆叠和源极/漏极区域上形成由难熔金属组成的第三层，并将第三层的至少一部分转化为第二金属硅化物区域。

4. 发明授权

US08698312B2 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging 有权
标题翻译：包括用于在包装期间和之后增强机械强度的混合金属化层堆叠的半导体器件
公开(公告)号：US08698312B2
公开(公告)日：2014-04-15
申请号：US11046986
申请日：2005-01-31
申请人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
发明人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
IPC分类号： H01L23/48
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.
摘要翻译：将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

5. 发明授权

US06261963B1 Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices 有权
标题翻译：阻挡金属层反向电镀以提高铜互连器件的电迁移性能
公开(公告)号：US06261963B1
公开(公告)日：2001-07-17
申请号：US09611729
申请日：2000-07-07
申请人： Larry Zhao , Paul R. Besser , Eric M. Apelgren , Christian Zistl , Jonathan B. Smith
发明人： Larry Zhao , Paul R. Besser , Eric M. Apelgren , Christian Zistl , Jonathan B. Smith
IPC分类号： H01L21302
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76829 , H01L21/76835 , H01L21/7684 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S438/927
摘要： A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.
摘要翻译：提供了一种用于形成导电互连的方法，所述方法包括在结构层上形成第一介电层，在第一介电层中形成第一开口，并在第一开口中形成第一导电结构。该方法还包括在第一介电层之上和第一导电结构之上形成第二电介质层，在第二导电结构的至少一部分上方的第二电介质层中形成第二开口，第二开口具有侧表面和并且在侧表面和底表面上的第二开口中形成至少一个阻挡金属层。此外，该方法包括从底表面去除至少一个阻挡金属层的一部分，以及在第二开口中形成第二导电结构，第二导电结构与第一导电结构的至少一部分接触。该方法还包括通过使第二导电结构和第一导电结构退火来形成导电互连。

6. 发明授权

US07416992B2 Method of patterning a low-k dielectric using a hard mask 有权
标题翻译：使用硬掩模图案化低k电介质的方法
公开(公告)号：US07416992B2
公开(公告)日：2008-08-26
申请号：US11287632
申请日：2005-11-28
申请人： Matthias Lehr , Peter Huebler , Christian Zistl
发明人： Matthias Lehr , Peter Huebler , Christian Zistl
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/3146 , H01L21/76808 , H01L21/7681 , Y10S438/952
摘要： By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.
摘要翻译：通过使用用于构图先进半导体器件的低k电介质材料的非金属硬掩模，获得了更高程度的蚀刻保真度。本发明可以容易地应用于通过第一沟槽最后沟槽第一通孔最后方案。

7. 发明授权

US07005380B2 Simultaneous formation of device and backside contacts on wafers having a buried insulator layer 有权
标题翻译：在具有掩埋绝缘体层的晶片上同时形成器件和背面触点
公开(公告)号：US07005380B2
公开(公告)日：2006-02-28
申请号：US10446974
申请日：2003-05-28
申请人： Massud Aminpur , Gert Burbach , Christian Zistl
发明人： Massud Aminpur , Gert Burbach , Christian Zistl
IPC分类号： H01L21/302
CPC分类号： H01L21/743 , H01L21/76802 , H01L21/76838 , H01L21/84 , H01L27/1203 , Y10S438/96
摘要： A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.
摘要翻译：提供一种半导体器件制造方法，其中在包括背面半导体衬底，埋入绝缘体层和顶部半导体层的晶片的顶部上形成器件结构。然后，在承载器件结构的晶片上形成蚀刻停止层，并且在蚀刻停止层中形成窗口。此外，在具有窗口的蚀刻停止层上形成介电层。然后，通过电介质层和向下到半导体衬底的窗口的第一接触孔同时被至少一个通过介电层的第二接触孔蚀刻到器件结构。晶片可以是绝缘体上硅（SOI）晶片，并且蚀刻停止层和电介质层可以分别通过沉积氮氧化硅和原硅酸四乙酯（TEOS）来形成。器件结构可以是CMOS晶体管结构。

8. 发明申请

US20050242435A1 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging 有权
标题翻译：包括用于在包装期间和之后增强机械强度的混合金属化层堆叠的半导体器件
公开(公告)号：US20050242435A1
公开(公告)日：2005-11-03
申请号：US11046986
申请日：2005-01-31
申请人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
发明人： James Werking , Frank Feustel , Christian Zistl , Peter Huebler
IPC分类号： H01L21/4763 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/50 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.
摘要翻译：将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

9. 发明授权

US07737021B1 Resist trim process to define small openings in dielectric layers 有权
标题翻译：抵抗修整过程以限定电介质层中的小开口
公开(公告)号：US07737021B1
公开(公告)日：2010-06-15
申请号：US10261613
申请日：2002-09-30
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料。

10. 发明申请

US20060246711A1 Method of patterning a low-k dielectric using a hard mask 有权
标题翻译：使用硬掩模图案化低k电介质的方法
公开(公告)号：US20060246711A1
公开(公告)日：2006-11-02
申请号：US11287632
申请日：2005-11-28
申请人： Matthias Lehr , Peter Huebler , Christian Zistl
发明人： Matthias Lehr , Peter Huebler , Christian Zistl
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/3146 , H01L21/76808 , H01L21/7681 , Y10S438/952
摘要： By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.
摘要翻译：通过使用用于构图先进半导体器件的低k电介质材料的非金属硬掩模，获得了更高程度的蚀刻保真度。本发明可以容易地应用于通过第一沟槽最后沟槽第一通孔最后方案。

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