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1. 发明授权

US5890214A Dynamically upgradeable disk array chassis and method for dynamically upgrading a data storage system utilizing a selectively switchable shunt 失效
标题翻译：动态可升级的磁盘阵列机箱和方法，用于使用可选择切换的分流器动态升级数据存储系统
公开(公告)号：US5890214A
公开(公告)日：1999-03-30
申请号：US748884
申请日：1996-11-14
申请人： James W. Espy , Jeffrey A. Brown , Scott J. Bleiweiss , Thomas B. Hawkins
发明人： James W. Espy , Jeffrey A. Brown , Scott J. Bleiweiss , Thomas B. Hawkins
IPC分类号： G06F11/30 , G06F13/40 , H04L5/20 , G06F13/00 , G06F11/20
CPC分类号： H04L5/20 , G06F11/3034 , G06F11/3044 , G06F11/3051 , G06F11/3058 , G06F13/409
摘要： A dynamically upgradeable disk array chassis, and a method for dynamically upgrading a data storage system. The dynamically upgradeable disk array chassis includes a serial bus having a first bus for passing data in one direction and a second bus for passing data in the opposite direction. A shunt connects the first and second buses in a normal state. The shunt has a switched state in which each of the first and second buses is coupled to a separate output from the chassis. The chassis includes an environmental monitor connected to a communication path. Upon connecting a new disk array chassis to an active disk array chassis, the environmental monitor communicates through the communication path before switching the shunt to connect the serial bus with the serial bus of the new disk array chassis. The disk array chassis may include a diplexer for connecting the communication path to the separate outputs of the shunt and for combining the communication path signals with the serial path signals in one direction and for separating these signals in the other direction. The environmental monitor path communications and the serial bus communications can take place over a single twinax cable.
摘要翻译：动态可升级的磁盘阵列机箱，以及动态升级数据存储系统的方法。动态可升级的磁盘阵列机箱包括具有用于在一个方向上传递数据的第一总线的串行总线和用于相反方向传递数据的第二总线。分流器在正常状态下连接第一和第二总线。分流器具有开关状态，其中第一和第二总线中的每一个耦合到与机架的单独输出。底盘包括连接到通信路径的环境监视器。在将新的磁盘阵列机箱连接到活动磁盘阵列机箱之后，环境监视器在切换分流器之前通过通信路径进行通信，以将串行总线与新磁盘阵列机箱的串行总线连接。盘阵列机箱可以包括用于将通信路径连接到分流器的单独输出的双工器，并且用于将通信路径信号与一个方向上的串行路径信号组合，并且用于在另一个方向上分离这些信号。环境监控通道和串行总线通信可以通过单个双芯电缆进行。

2. 发明授权

US5901151A System for orthogonal signal multiplexing 失效
标题翻译：正交信号复用系统
公开(公告)号：US5901151A
公开(公告)日：1999-05-04
申请号：US801603
申请日：1997-02-13
申请人： Scott J. Bleiweiss , Thomas B. Hawkins , James W. Espy
发明人： Scott J. Bleiweiss , Thomas B. Hawkins , James W. Espy
IPC分类号： G06F13/10 , G06F3/06 , G06F11/30 , G06F12/16 , G06F13/00 , G06F13/38 , G06F13/40 , H04L5/20 , H04J1/08 , H04J1/16 , H04L12/26
CPC分类号： G06F11/3058 , G06F11/3034 , G06F11/3041 , G06F11/3051 , G06F11/3055 , G06F13/409 , H04L5/20
摘要： A high frequency signal and a low frequency signal are coupled onto a pair of conductors providing a communication link between two computer components. The high frequency signal may be a differentially coupled Fibre Channel 8B/10B encoded signal. A diplexer includes a low pass filter for attenuating the Fibre Channel signal and a high pass filter for separately attenuating the low frequency signal. A two-way communication link may be provided over twinax cable. An environmental monitor may be in connection with the low frequency communication path.
摘要翻译：高频信号和低频信号被耦合到一对导体上，提供两个计算机组件之间的通信链路。高频信号可以是差分耦合的光纤通道8B / 10B编码信号。双工器包括用于衰减光纤通道信号的低通滤波器和用于单独衰减低频信号的高通滤波器。双向通信链路可以通过双轴电缆提供。环境监视器可以与低频通信路径相关联。

3. 发明授权

US5734388A Method and apparatus for data compression of digital data to produce a scaleable font database 失效
标题翻译：用于数字数据的数据压缩以产生可缩放字体数据库的方法和装置
公开(公告)号：US5734388A
公开(公告)日：1998-03-31
申请号：US242950
申请日：1994-05-16
申请人： Allan W. Ristow , Thomas B. Hawkins
发明人： Allan W. Ristow , Thomas B. Hawkins
IPC分类号： G09G5/24 , G06F17/21 , G06K15/02 , G06T11/20 , G06T11/00
CPC分类号： G06T11/203 , G06K15/02 , G06K2215/0028 , G06K2215/0042
摘要： A method and apparatus for storing scaleable font data in a compact form and retrieving it in one of several usable forms common in digital typography. The retrieval process can be influenced by parameters to produce not only the original typeface designs that were compressed, but also variations on those typeface designs. Variations produced in this manner are related typeface designs which therefore effectively add new fonts to the family originally stored. Individual character pixelmaps and scaleable character outlines are two of the forms which can be retrieved from the compressed font data. The storage and retrieval methods are designed so that the time needed to produce a single character pixelmap from the internal form is less than that required for producing the same pixelmap from an uncompressed hinted outline font stored in an industry-standard format.
摘要翻译：用于以紧凑形式存储可缩放字体数据并以数字印刷中常见的几种可用形式之一检索它的方法和装置。检索过程可能受到参数的影响，不仅产生了被压缩的原始字体设计，而且还产生了这些字体设计上的变体。以这种方式产生的变化是相关的字体设计，因此有效地将新字体添加到原来存储的家庭中。单个字符像素图和可缩放字符轮廓是可从压缩字体数据中检索的两种形式。存储和检索方法被设计为使得从内部形式产生单个字符像素图所需的时间小于从以行业标准格式存储的未压缩暗示轮廓字体生成相同像素图所需的时间。

4. 发明授权

US5754187A Method for data compression of digital data to produce a scaleable font database 失效
标题翻译：用于数字数据压缩以产生可缩放字体数据库的方法
公开(公告)号：US5754187A
公开(公告)日：1998-05-19
申请号：US242941
申请日：1994-05-16
申请人： Allan W. Ristow , Thomas B. Hawkins
发明人： Allan W. Ristow , Thomas B. Hawkins
IPC分类号： B41J2/485 , G06F17/21 , G06K15/02 , G06T11/20 , G09G5/24 , G06T11/00
CPC分类号： G06T11/203 , G06K15/02 , G06K2215/0034
摘要： A method for construction of a scaleable font database comprised of data stored in a compact form for retrieval in one of several usable forms common in digital typography. The method comprises the steps, for each text character of a font collection of: generating a digital representation of the character and identifying it with respect to character code and typeface design, determining segment endpoints and associations within a model of the character, measuring actual dimensions for the associations, and determining segment descriptors for each contour segment comprising the complete outline of the character.
摘要翻译：一种用于构建可缩放字体数据库的方法，包括以紧凑形式存储的数据，用于以数字印刷中常见的几种可用形式之一进行检索。该方法包括以下步骤：对于字体集合的每个文本字符，生成字符的数字表示，并且相对于字符代码和字体设计识别它，确定字符模型内的段端点和关联，测量实际尺寸并且为每个包括字符的完整轮廓的轮廓段确定段描述符。

5. 发明授权

US5539345A Phase detector apparatus 失效
标题翻译：相位检测装置
公开(公告)号：US5539345A
公开(公告)日：1996-07-23
申请号：US998977
申请日：1992-12-30
申请人： Thomas B. Hawkins
发明人： Thomas B. Hawkins
IPC分类号： G06F1/12 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/22 , G06F13/28 , G06F13/42 , H03D13/00 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/06
CPC分类号： G06F1/12 , G06F11/1633 , G06F11/1645 , G06F11/1658 , G06F11/1679 , G06F11/1683 , G06F13/28 , G06F13/4243 , H03L7/085 , H03L7/087 , G06F11/006 , G06F11/1008 , G06F11/1044 , G06F11/1604 , G06F11/1654 , G06F11/20 , G06F11/2205 , H03D13/003 , H03L7/089
摘要： A fault tolerant computer according to the invention includes a processing unit including a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second, abbreviated system bus to receive read data from said first system bus. Coupled to said processing unit is an Input/Output device for interfacing to external devices. The processing unit includes a phase detector apparatus for aligning a clock of the processor unit to that of the Input/Output unit to facilitate data transfer. The phase detector apparatus includes a first means for providing a first clocking signal related to the clocking signal of the Input/Output unit, and a second means for providing a second clocking signal related to the clocking signal of the processor unit. The phase detector apparatus further includes means for providing an error signal responsive to an offset between edges of the first and second clocking signals.
摘要翻译：根据本发明的容错计算机包括处理单元，该处理单元包括耦合到第一系统总线以向高速缓存和存储器提供数据的第一处理器，以及耦合到第一系统总线的第二处理器和第二简化系统总线从所述第一系统总线接收读取数据。耦合到所述处理单元是用于与外部设备接口的输入/输出设备。处理单元包括相位检测器装置，用于将处理器单元的时钟与输入/输出单元的时钟对准，以便于数据传送。相位检测器装置包括用于提供与输入/输出单元的时钟信号有关的第一时钟信号的第一装置和用于提供与处理器单元的时钟信号相关的第二时钟信号的第二装置。相位检测器装置还包括用于响应于第一和第二计时信号的边沿之间的偏移而提供误差信号的装置。

6. 发明授权

US4675830A Method for producing a scaleable typeface data 失效
标题翻译：用于生成可缩放字体数据的方法
公开(公告)号：US4675830A
公开(公告)日：1987-06-23
申请号：US628192
申请日：1984-07-06
申请人： Thomas B. Hawkins
发明人： Thomas B. Hawkins
IPC分类号： G06F3/153 , G06T9/20 , G09G5/24 , G06F15/20
CPC分类号： G06T9/20
摘要： A method for producing scaleable contour data that is capable of providing: (1) bit-map font data at any resolution and at any point size and, (2) grid aligned contours for output to contour driven devices such as, pen plotters and numerically controlled machines, is disclosed. The method "stretches" and "compresses" character contours to bring specified contour points ("Skeletal Points") into proper alignment with the "bit-map grid". The mathematical basis for the method is one of (1) breaking the character contour into segments (between a pair of Skeletal Points), (2) offsetting all coordinates in the segment to bring the first Skeletal Point to align with the grid, and finally, (3) linear scaling of the segment with a scale factor which brings the second Skeletal Point to align with the grid.
摘要翻译：一种用于产生可扩展轮廓数据的方法，其能够提供：（1）以任何分辨率和任何点大小的位图字体数据，以及（2）网格对齐轮廓，用于输出到轮廓驱动装置，例如笔式绘图仪和数字受控机器被公开。方法“拉伸”和“压缩”字符轮廓，以使指定的轮廓点（“骨架点”）与“位图网格”正确对齐。该方法的数学基础是（1）将字符轮廓分解为段（一对骨骼点之间），（2）抵消段中的所有坐标，使第一个骨架点与网格对齐，最后，（3）使用缩放因子对片段进行线性缩放，从而使第二个骨架点与网格对齐。

7. 发明授权

US07184046B1 Method and apparatus for font storage reduction 有权
标题翻译：减少字体存储的方法和装置
公开(公告)号：US07184046B1
公开(公告)日：2007-02-27
申请号：US09407381
申请日：1999-09-28
申请人： Thomas B. Hawkins
发明人： Thomas B. Hawkins
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： The present invention is aimed at three specific data areas of font compression, each of whose size has become significant as other data areas have been compressed. The three data areas include model factoring, character level feature measurement (local dimensions) factoring, and typeface level feature measurement (global dimensions) factoring. In general, the invention in each area is an apparatus and method used in font compression to reduce redundant information, thereby allowing a reduction in data format (e.g., words to bytes and bytes to bits) resulting in an overall reduction in storage area for a given font collection.
摘要翻译：本发明针对字体压缩的三个特定数据区域，其中的每个尺寸随着其他数据区域被压缩而变大。三个数据区域包括模型分解，字符级特征测量（局部维度）因式分解和字体水平特征测量（全局维度）分解。通常，每个区域中的本发明是用于字体压缩以减少冗余信息的装置和方法，从而允许将数据格式（例如，字到字节和字节到位）减少，从而导致对于给定字体集合。

8. 发明授权

US5408640A Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes 失效
标题翻译：相位延迟补偿器，使用由同步器产生的门控信号，用于加载和移位位模式以产生与频率变化相对应的时钟相位
公开(公告)号：US5408640A
公开(公告)日：1995-04-18
申请号：US995311
申请日：1992-12-22
申请人： Douglas A. MacIntyre , Thomas B. Hawkins
发明人： Douglas A. MacIntyre , Thomas B. Hawkins
IPC分类号： G06F1/08 , G06F1/04 , G06F1/06 , G06F1/12
CPC分类号： G06F1/08
摘要： A phase delay compensator apparatus is provided which compensates for the phase error caused by propagation delay differences between clock and data paths within a computer system. A look-up table circuit is used to dynamically translate a change in frequency of the computer system clock or a change in the length of cable connecting the computer's sub-assemblies to a binary bit pattern defining the requisite phase-shift between distributed clock and data signals. A generator circuit produces phases of the phase-shifted clock signals, while ensuring the integrity of the loaded binary bit pattern. A gated signal is created for enabling the generator circuit.
摘要翻译：提供了相位延迟补偿器装置，其补偿由计算机系统内的时钟和数据路径之间的传播延迟差导致的相位误差。查找表电路用于动态地转换计算机系统时钟的频率变化或连接计算机的子组件的电缆长度的变化，以二进制位模式定义分布式时钟和数据之间必需的相移信号。发电机电路产生相移时钟信号的相位，同时确保加载的二进制位模式的完整性。创建门控信号用于启用发电机电路。

9. 发明授权

US5347559A Apparatus and method of data transfer between systems using different clocks 失效
标题翻译：使用不同时钟的系统之间的数据传输的装置和方法
公开(公告)号：US5347559A
公开(公告)日：1994-09-13
申请号：US998714
申请日：1992-12-30
申请人： Thomas B. Hawkins , William Bruckert , Thomas D. Bissett
发明人： Thomas B. Hawkins , William Bruckert , Thomas D. Bissett
IPC分类号： G06F1/12 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/22 , G06F13/28 , G06F13/42 , H03D13/00 , H03L7/085 , H03L7/087 , H03L7/089 , H03K21/08
CPC分类号： G06F1/12 , G06F11/1633 , G06F11/1645 , G06F11/1658 , G06F11/1679 , G06F11/1683 , G06F13/28 , G06F13/4243 , H03L7/085 , H03L7/087 , G06F11/006 , G06F11/1008 , G06F11/1044 , G06F11/1604 , G06F11/1654 , G06F11/20 , G06F11/2205 , H03D13/003 , H03L7/089
摘要： According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.
摘要翻译：根据本发明的一个方面，一种装置包括耦合到第一系统总线以向高速缓存和存储器提供数据的第一处理器，以及耦合到第一系统总线的第二处理器和用于接收读取数据的第二缩写系统总线从第一个系统总线。根据本发明的另一方面，一种装置包括用于校正存储器中的错误的装置。根据本发明的另一方面，一种装置包括多个计算系统，每个计算系统包括安装在不经常更换的硬件单元上并且能够与多个计算系统进行通信的存储器装置。根据本发明的另一方面，一种装置包括计数器，用于检测所述计数器的选定状态的装置，以及响应于来自所述计数器的输出信号的装置，用于选择性地允许或禁止馈送到循环状态装置的数据的传送。根据本发明的另一方面，一种装置包括用于提供第一时钟信号的第一装置，用于提供第二时钟信号的第二装置，用于响应于第一和第二时钟信号的边缘之间的偏移而提供误差信号的装置时钟信号。

10. 发明授权

US5164677A Method and apparatus for synchronizing signals 失效
标题翻译：用于同步信号的方法和装置
公开(公告)号：US5164677A
公开(公告)日：1992-11-17
申请号：US740457
申请日：1991-08-05
申请人： Thomas B. Hawkins , Douglas A. MacIntyre , Johannes A. S. Bjorner
发明人： Thomas B. Hawkins , Douglas A. MacIntyre , Johannes A. S. Bjorner
IPC分类号： H03H7/34
CPC分类号： H03H7/345
摘要： A method and apparatus for synchronizing two signals having a phase relationship and originating from transmission lines having unknown and differing skew includes a variable delay element with adjustable delay responsive to an applied biasing voltage inserted into one of the transmission lines. The phases of the signals are compared and phase error information generated. The error information is thereafter converted to a biasing voltage which is applied to the variable delay element. As a result, the delay characteristic of the one transmission line is adjusted to synchronize the signals.
摘要翻译：用于同步具有相位关系并且源自具有未知和不同偏斜的传输线的两个信号的方法和装置包括响应于插入到一个传输线中的施加的偏置电压的具有可调延迟的可变延迟元件。比较信号的相位和产生的相位误差信息。然后将误差信息转换成施加到可变延迟元件的偏置电压。结果，调整一条传输线的延迟特性以使信号同步。

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