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1. 发明授权

US07446007B2 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof 失效
标题翻译：具有抑制凹陷/底切的多层间隔物及其制造方法
公开(公告)号：US07446007B2
公开(公告)日：2008-11-04
申请号：US11560893
申请日：2006-11-17
申请人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
发明人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
摘要翻译：半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。因此确保了多层间隔层的尺寸完整性和分层避免。

2. 发明申请

US20080116493A1 MULTI-LAYER SPACER WITH INHIBITED RECESS/UNDERCUT AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：具有禁止记忆的多层隔板及其制造方法
公开(公告)号：US20080116493A1
公开(公告)日：2008-05-22
申请号：US11560893
申请日：2006-11-17
申请人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart , Dale W. Martin
发明人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart , Dale W. Martin
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
摘要翻译：半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。因此确保了多层间隔层的尺寸完整性和分层避免。

3. 发明授权

US07303952B2 Method for fabricating doped polysilicon lines 有权
标题翻译：掺杂多晶硅生产线的制造方法
公开(公告)号：US07303952B2
公开(公告)日：2007-12-04
申请号：US10711771
申请日：2004-10-04
申请人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
发明人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

4. 发明授权

US09058455B2 Backside integration of RF filters for RF front end modules and design structure 有权
标题翻译：用于RF前端模块的RF滤波器的背面集成和设计结构
公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译：在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

5. 发明申请

US20150041904A1 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING 有权
标题翻译：空心短路通道带有非直线长通道补偿的通道拉伸通过图案打开进行植入
公开(公告)号：US20150041904A1
公开(公告)日：2015-02-12
申请号：US14493749
申请日：2014-09-23
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/10 , H01L29/36 , H01L29/08 , H01L29/78
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
摘要翻译：一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口。保形介电层覆盖衬底的沟道区。该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

6. 发明授权

US08743247B2 Low lag transfer gate device 有权
标题翻译：低延迟传输门装置
公开(公告)号：US08743247B2
公开(公告)日：2014-06-03
申请号：US12013826
申请日：2008-01-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
IPC分类号： H04N3/14 , H01L31/062
CPC分类号： H01L31/103 , H04N5/353 , H04N5/374 , H04N5/3745
摘要： A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.
摘要翻译：一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

7. 发明授权

US08610174B2 Bipolar transistor with a raised collector pedestal for reduced capacitance 有权
标题翻译：双极晶体管带有集电极基座，用于降低电容
公开(公告)号：US08610174B2
公开(公告)日：2013-12-17
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L31/109
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了具有降低的集电极基座的晶体管，用于减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

8. 发明授权

US08440490B2 CMOS imager photodiode with enhanced capacitance 有权
标题翻译：具有增强电容的CMOS成像光电二极管
公开(公告)号：US08440490B2
公开(公告)日：2013-05-14
申请号：US13288686
申请日：2011-11-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/18
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.
摘要翻译：一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。表面注入层形成在具有第一导电类型材料的沟槽的任一侧。沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

9. 发明授权

US08039875B2 Structure for pixel sensor cell that collects electrons and holes 失效
标题翻译：用于收集电子和空穴的像素传感器单元的结构
公开(公告)号：US08039875B2
公开(公告)日：2011-10-18
申请号：US11850776
申请日：2007-09-06
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D Jaffe , Jeffrey B. Johnson , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D Jaffe , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L27/148 , H01L31/062
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

10. 发明授权

US08003425B2 Methods for forming anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器形成抗反射结构的方法
公开(公告)号：US08003425B2
公开(公告)日：2011-08-23
申请号：US12120459
申请日：2008-05-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

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