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1. 发明授权

US07446007B2 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof 失效
标题翻译：具有抑制凹陷/底切的多层间隔物及其制造方法
公开(公告)号：US07446007B2
公开(公告)日：2008-11-04
申请号：US11560893
申请日：2006-11-17
申请人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
发明人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart, III , Dale W. Martin
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
摘要翻译：半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。因此确保了多层间隔层的尺寸完整性和分层避免。

2. 发明申请

US20080116493A1 MULTI-LAYER SPACER WITH INHIBITED RECESS/UNDERCUT AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：具有禁止记忆的多层隔板及其制造方法
公开(公告)号：US20080116493A1
公开(公告)日：2008-05-22
申请号：US11560893
申请日：2006-11-17
申请人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart , Dale W. Martin
发明人： James W. Adkisson , Marc W. Cantell , James R. Elliott , James V. Hart , Dale W. Martin
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
摘要翻译：半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。因此确保了多层间隔层的尺寸完整性和分层避免。

3. 发明授权

US07303952B2 Method for fabricating doped polysilicon lines 有权
标题翻译：掺杂多晶硅生产线的制造方法
公开(公告)号：US07303952B2
公开(公告)日：2007-12-04
申请号：US10711771
申请日：2004-10-04
申请人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
发明人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

4. 发明授权

US07378712B2 Gate stacks 有权
标题翻译：门堆叠
公开(公告)号：US07378712B2
公开(公告)日：2008-05-27
申请号：US11463039
申请日：2006-08-08
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.
摘要翻译：门堆栈结构。该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域并掺杂一种掺杂剂。该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止含氧材料通过扩散阻挡区扩散。

5. 发明授权

US5926708A Method for providing multiple gate oxide thicknesses on the same wafer 失效
标题翻译：在同一晶片上提供多个栅极氧化物厚度的方法
公开(公告)号：US5926708A
公开(公告)日：1999-07-20
申请号：US859588
申请日：1997-05-20
申请人： Dale W. Martin
发明人： Dale W. Martin
IPC分类号： H01L21/8234 , H01L21/8242
CPC分类号： H01L21/823462
摘要： The present invention is directed to a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. The method includes the steps of growing a first oxide layer on a substrate, depositing a first polysilicon layer over the first oxide layer, applying a block mask, etching the first polysilicon layer, stripping the block mask, stripping the first oxide layer from the areas opened by the block mask, growing a second oxide layer, depositing a second polysilicon layer, and polishing the second polysilicon layer to remove the second polysilicon layer from everywhere except the areas opened by the block mask. If desired, a polish stop layer may be deposited after depositing the first polysilicon layer. Threshold implants may also be made after the block mask is stripped. Finally, polysilicon shapes may be added to the boundary areas opened by the block mask to help eliminate foreign material problems.
摘要翻译：本发明涉及在同一晶片上制造具有两个或多个栅极氧化物厚度的集成电路的方法。该方法包括以下步骤：在衬底上生长第一氧化物层，在第一氧化物层上沉积第一多晶硅层，施加阻挡掩模，蚀刻第一多晶硅层，剥离阻挡掩模，从区域剥离第一氧化物层通过块掩模打开，生长第二氧化物层，沉积第二多晶硅层，以及抛光第二多晶硅层以除去由阻挡掩模打开的区域以外的任何地方的第二多晶硅层。如果需要，可以在沉积第一多晶硅层之后沉积抛光停止层。剥离块掩模后也可以进行阈值植入。最后，可以将多晶硅形状添加到通过阻挡掩模打开的边界区域，以帮助消除异物问题。

6. 发明授权

US08778737B2 Flattened substrate surface for substrate bonding 有权
标题翻译：用于衬底粘合的平坦化衬底表面
公开(公告)号：US08778737B2
公开(公告)日：2014-07-15
申请号：US13285443
申请日：2011-10-31
申请人： Edward C. Cooney, III , James S. Dunn , Dale W. Martin , Charles F. Musante , BethAnn Rainey , Leathen Shi , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Edward C. Cooney, III , James S. Dunn , Dale W. Martin , Charles F. Musante , BethAnn Rainey , Leathen Shi , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L21/00 , H01L29/10
CPC分类号： H01L23/4825 , H01L21/6835 , H01L21/76819 , H01L22/32 , H01L22/34 , H01L23/5223 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L29/1054 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/0361 , H01L2224/0401 , H01L2224/05166 , H01L2224/05187 , H01L2224/05567 , H01L2224/05624 , H01L2224/05687 , H01L2224/06181 , H01L2224/08225 , H01L2224/131 , H01L2224/73251 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80203 , H01L2224/804 , H01L2224/80487 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/014 , H01L2224/08 , H01L2224/16 , H01L2924/05432 , H01L2924/053 , H01L2924/01031 , H01L2924/01033 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
摘要翻译：用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。使用器件基板的第一表面形成产品芯片的器件结构。在产品芯片上形成用于器件结构的互连结构的布线层。布线层被平坦化。临时处理晶片可移除地结合到平坦化的布线层。响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。然后将临时手柄晶片从组件中取出。

7. 发明授权

US07157341B2 Gate stacks 失效
标题翻译：门堆叠
公开(公告)号：US07157341B2
公开(公告)日：2007-01-02
申请号：US10711742
申请日：2004-10-01
申请人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
发明人： Dale W. Martin , Steven M. Shank , Michael C. Triplett , Deborah A. Tucker
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.
摘要翻译：用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。

8. 发明授权

US06525371B2 Self-aligned non-volatile random access memory cell and process to make the same 有权
标题翻译：自对准非易失性随机存取存储器单元和过程相同
公开(公告)号：US06525371B2
公开(公告)日：2003-02-25
申请号：US09401622
申请日：1999-09-22
申请人： Jeffrey B. Johnson , Chung H. Lam , Dana Lee , Dale W. Martin , Jed H. Rankin
发明人： Jeffrey B. Johnson , Chung H. Lam , Dana Lee , Dale W. Martin , Jed H. Rankin
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.
摘要翻译：在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法在基板上具有基本上彼此平行的多个间隔开的隔离区域。有源区域位于每对相邻隔离区域之间。活性隔离区域和平行区域形成为平行且在列方向。在行方向上，形成间隔开的氮化硅的条。源极线插塞形成在相邻的氮化硅对之间并且与有源区域中的第一区域以及隔离区域接触。去除氮化硅条并进行各向同性蚀刻。此外，氮化硅下方的材料也被各向同性地蚀刻。然后在平行于源极线插塞并与浮动栅极相邻的行方向上形成多晶硅间隔物，以形成连接的控制栅极。第二区域形成在相邻的间隔开的控制门之间。在与控制栅极之间的空间中的第二区域接触的位线方向上形成位线。

9. 发明授权

US06949458B2 Self-aligned contact areas for sidewall image transfer formed conductors 失效
标题翻译：用于侧壁图像传输形成的导体的自对准接触区域
公开(公告)号：US06949458B2
公开(公告)日：2005-09-27
申请号：US10361228
申请日：2003-02-10
申请人： Edward W. Conrad , Chung H. Lam , Dale W. Martin , Edmund Sprogis
发明人： Edward W. Conrad , Chung H. Lam , Dale W. Martin , Edmund Sprogis
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76895 , H01L23/485 , H01L2924/0002 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.
摘要翻译：用于形成具有接触焊盘的侧壁图像传送导体的方法和结构包括形成绝缘体以包括凹部，在绝缘体周围沉积导体，并蚀刻导体以形成侧壁图像传输导体，其中导体保留在凹部并且形成接触焊盘，并且凹部垂直于侧壁图像传送导体。

10. 发明授权

US06566759B1 Self-aligned contact areas for sidewall image transfer formed conductors 有权
标题翻译：用于侧壁图像传输形成的导体的自对准接触区域
公开(公告)号：US06566759B1
公开(公告)日：2003-05-20
申请号：US09379453
申请日：1999-08-23
申请人： Edward W. Conrad , Chung H. Lam , Dale W. Martin , Edmund Sprogis
发明人： Edward W. Conrad , Chung H. Lam , Dale W. Martin , Edmund Sprogis
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76895 , H01L23/485 , H01L2924/0002 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.
摘要翻译：用于形成具有接触焊盘的侧壁图像传送导体的结构包括形成绝缘体以包括凹部，在绝缘体周围沉积导体，并蚀刻导体以形成侧壁图像传输导体，其中导体保留在凹部中并形成接触垫和凹部垂直于侧壁图像传送导体。

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