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1. 发明授权

US5796992A Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode 失效
标题翻译：用于在低功耗模式下在同步和异步存储器刷新周期之间切换的电路
公开(公告)号：US5796992A
公开(公告)日：1998-08-18
申请号：US575370
申请日：1995-12-20
申请人： James R. Reif , Michael J. Collins , Todd J. DeSchepper
发明人： James R. Reif , Michael J. Collins , Todd J. DeSchepper
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/32
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。

2. 发明授权

US5721935A Apparatus and method for entering low power mode in a computer system 失效
标题翻译：在计算机系统中进入低功率模式的装置和方法
公开(公告)号：US5721935A
公开(公告)日：1998-02-24
申请号：US801200
申请日：1997-02-18
申请人： Todd J. DeSchepper , James R. Reif , James R. Edwards , Michael J. Collins , John E. Larson
发明人： Todd J. DeSchepper , James R. Reif , James R. Edwards , Michael J. Collins , John E. Larson
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。

3. 发明授权

US5740454A Circuit for setting computer system bus signals to predetermined states in low power mode 失效
标题翻译：用于在低功率模式下将计算机系统总线信号设置为预定状态的电路
公开(公告)号：US5740454A
公开(公告)日：1998-04-14
申请号：US576193
申请日：1995-12-20
申请人： Philip C. Kelly , Todd J. DeSchepper , James R. Reif
发明人： Philip C. Kelly , Todd J. DeSchepper , James R. Reif
IPC分类号： G06F1/32
CPC分类号： G06F1/3228
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STAND BY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和STAND BY模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。

4. 发明授权

US06357013B1 Circuit for setting computer system bus signals to predetermined states in low power mode 失效
标题翻译：用于在低功率模式下将计算机系统总线信号设置为预定状态的电路
公开(公告)号：US06357013B1
公开(公告)日：2002-03-12
申请号：US09042914
申请日：1998-03-17
申请人： Philip C. Kelly , Todd J. DeSchepper , James R. Reif
发明人： Philip C. Kelly , Todd J. DeSchepper , James R. Reif
IPC分类号： G06F132
CPC分类号： G06F1/3228
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。

5. 发明授权

US06199131B1 Computer system employing optimized delayed transaction arbitration technique 失效
公开(公告)号：US06199131B1
公开(公告)日：2001-03-06
申请号：US08995699
申请日：1997-12-22
申请人： Maria L. Melo , Khaldoun Alzien , Todd J. DeSchepper
发明人： Maria L. Melo , Khaldoun Alzien , Todd J. DeSchepper
IPC分类号： G06F1300
CPC分类号： G06F13/362 , G06F13/4031
摘要： A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.

6. 发明授权

US5987555A Dynamic delayed transaction discard counter in a bus bridge of a computer system 失效
标题翻译：计算机系统总线桥中的动态延迟事务丢弃计数器
公开(公告)号：US5987555A
公开(公告)日：1999-11-16
申请号：US995386
申请日：1997-12-22
申请人： Khaldoun Alzien , Maria L. Melo , Todd J. DeSchepper
发明人： Khaldoun Alzien , Maria L. Melo , Todd J. DeSchepper
IPC分类号： G06F13/40 , G06F13/00 , G06F13/20
CPC分类号： G06F13/4031
摘要： A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.
摘要翻译： PCI桥被配置为响应于在PCI总线上发起的存储器读取而执行延迟读取操作。通常，PCI桥被配置为在PCI主机建立延迟读取操作在PCI总线上重试之后的预定丢弃计数时间之后丢弃从主存储器读取的延迟读取数据。计算机系统还包括辅助总线桥，例如ISA桥，用于提供PCI总线和ISA总线之间的接口。当ISA设备希望从主存储器读取数据时，ISA桥断言刷新请求信号。 PCI桥接器响应性地将任何待处理的CPU刷新到PCI桥内待处理的PCI事务。当冲洗操作完成时，PCI桥断言一个确认信号。用于仲裁PCI总线的所有权的PCI仲裁器可以响应于确认信号的断言而增加提供给ISA桥的仲裁优先级。有利地，PCI桥被配置为当确认确认信号被断言时，减少与丢弃延迟的读取数据相关联的时间。

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