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1. 发明申请

US20080177981A1 APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN INSTRUCTION CACHE AND A PIPELINE PROCESSOR 失效
标题翻译：指令缓存和管道处理器之间延迟延迟的装置和方法
公开(公告)号：US20080177981A1
公开(公告)日：2008-07-24
申请号：US11868557
申请日：2007-10-08
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

2. 发明授权

US07711930B2 Apparatus and method for decreasing the latency between instruction cache and a pipeline processor 失效
标题翻译：用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法
公开(公告)号：US07711930B2
公开(公告)日：2010-05-04
申请号：US11868557
申请日：2007-10-08
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

3. 发明授权

US07281120B2 Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor 失效
标题翻译：用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法
公开(公告)号：US07281120B2
公开(公告)日：2007-10-09
申请号：US10810235
申请日：2004-03-26
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

4. 发明授权

US07321954B2 Method for software controllable dynamically lockable cache line replacement system 有权
标题翻译：软件可控动态锁定缓存线替换系统的方法
公开(公告)号：US07321954B2
公开(公告)日：2008-01-22
申请号：US10915982
申请日：2004-08-11
申请人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F12/126 , G06F12/125
摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
摘要翻译：用于跟踪关联高速缓存行的访问的LRU数组和方法。缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。第二组数据识别一条路线是否不被替换。对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为锁定对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。

5. 发明申请

US20110047357A1 Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions 审中-公开
标题翻译：用于预测非执行条件非分支指令的方法和装置
公开(公告)号：US20110047357A1
公开(公告)日：2011-02-24
申请号：US12543847
申请日：2009-08-19
申请人： Brian M. Stempel , James N. Dieffenderfer , Thomas A. Sartorius , David J. Mandzak , Rodney W. Smith
发明人： Brian M. Stempel , James N. Dieffenderfer , Thomas A. Sartorius , David J. Mandzak , Rodney W. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/3832 , G06F9/3844 , G06F9/3861
摘要： Efficient techniques are described for not executing an issued conditional non-branch instruction. A conditional non-branch instruction is identified as being eligible for a prediction, the prediction indicating that the eligible conditional non-branch (ECNB) instruction would not execute. The ECNB instruction executes as a no operation (NOP) instruction in response to the prediction that the ECNB instruction would not execute. A source operand required for the ECNB instruction to execute is not fetched in response to the prediction to not execute.
摘要翻译：描述了不执行发出的条件非分支指令的高效技术。条件非分支指令被识别为有资格进行预测，该预测指示合格条件非分支（ECNB）指令将不执行。响应于ECNB指令不执行的预测，ECNB指令作为无操作（NOP）指令执行。 ECNB指令执行所需的源操作数不响应于不执行的预测而被取出。

6. 发明授权

US07395380B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07395380B2
公开(公告)日：2008-07-01
申请号：US10393116
申请日：2003-03-20
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

7. 发明授权

US5734600A Polynomial multiplier apparatus and method 失效
标题翻译：多项式乘法器装置及方法
公开(公告)号：US5734600A
公开(公告)日：1998-03-31
申请号：US219694
申请日：1994-03-29
申请人： James N. Dieffenderfer , James W. Dieffenderfer
发明人： James N. Dieffenderfer , James W. Dieffenderfer
IPC分类号： G06F7/52
CPC分类号： G06F7/5334 , G06F7/5336 , G06F7/5338
摘要： A multiplier efficiently multiplies signed or unsigned binary polynomial operands. The multiplier includes storage means for temporary storage of a current multiplier and a current multiplicand each of which being binary polynomials, one or more Booth decoders for examining multiplier bits iteratively in predetermined groups and presenting a Booth decoder output as one set of inputs to a plurality of delta generators and a partial product delta generator. Another set of inputs to the delta generators and the partial product delta generator is a predetermined group of bits from a multiplicand. The outputs of the partial product delta generator are multiplexed with outputs of the partial product register to provide inputs of an adder array. The adder array has outputs to a parallel adder which generates partial products which are then fed back to the multiplexor. The operation of the multiplier is controlled by a state machine wherein the multiplexor selects one of a plurality of inputs to the multiplexor as output depending upon the state condition of the state machine.
摘要翻译：乘数有效地乘以带符号或无符号的二进制多项式操作数。乘法器包括用于临时存储当前乘法器的存储装置和每个都是二进制多项式的当前乘法器，一个或多个布尔解码器，用于在预定组中迭代地检查乘法器位，并将布斯解码器输出作为一组输入提供给多个的三角洲发电机和部分产品增量发生器。来自增量发生器和部分乘积增量发生器的另一组输入是来自被乘数的预定比特组。部分乘积增量发生器的输出与部分乘积寄存器的输出复用，以提供加法器阵列的输入。加法器阵列具有输出到并行加法器，该并行加法器产生部分积，然后反馈给多路复用器。乘法器的操作由状态机控制，其中多路复用器根据状态机的状态来选择多路复用器的多个输入中的一个作为输出。

8. 发明授权

US5590372A VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers 失效
标题翻译： VME总线将系统广播修改器传输到多个设备，并且多个设备同时接收数据到修改器的数据，而无需确认修改器
公开(公告)号：US5590372A
公开(公告)日：1996-12-31
申请号：US913270
申请日：1992-07-14
申请人： James N. Dieffenderfer , Bruce J. Morehead
发明人： James N. Dieffenderfer , Bruce J. Morehead
IPC分类号： G06F13/42 , G06F12/02
CPC分类号： G06F13/4213
摘要： A method for synchronous broadcasting of multiple bytes over a VME bus broadcasts multiple bytes of data across the VME bus using hardware which interfaces between the bus and attached devices. An VME address modifier code is used to identify the type of broadcast and is sent by a master device, without requiring any response from the slave devices. In a first type of broadcast an address location is transmitted over the address bus and a data message is transmitted over the data bus. In a second type of broadcast data messages are transmitted over both the data and the address buses. Multiple broadcast cycles are used to transmit the desired amount of data. An address strobe qualifies the address and data buses for a message broadcast cycle and is used by the receiving slave to clock in the message.
摘要翻译：一种用于通过VME总线同步广播多个字节的方法通过使用总线和附加设备之间的接口的硬件在VME总线上广播多个字节的数据。 VME地址修改码用于标识广播的类型并由主设备发送，而不需要来自从设备的任何响应。在第一类广播中，通过地址总线传送地址位置，并通过数据总线发送数据消息。在第二种类型的广播数据消息通过数据和地址总线发送。使用多个广播周期来传送期望的数据量。地址选通符限定了消息广播周期的地址和数据总线，并且被接收从机用于消息中的时钟。

9. 发明授权

US07685373B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07685373B2
公开(公告)日：2010-03-23
申请号：US11970599
申请日：2008-01-08
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

10. 发明授权

US06826747B1 System and method for tracing program instructions before and after a trace triggering event within a processor 失效
标题翻译：在处理器内跟踪触发事件之前和之后跟踪程序指令的系统和方法
公开(公告)号：US06826747B1
公开(公告)日：2004-11-30
申请号：US09412124
申请日：1999-10-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F1130
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event, and then providing the trace information externally from the processor.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令，然后从处理器向外部提供跟踪信息。

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