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1. 发明授权

US08667192B2 Integrated circuit with programmable circuitry and an embedded processor system 有权
标题翻译：具有可编程电路和嵌入式处理器系统的集成电路
公开(公告)号：US08667192B2
公开(公告)日：2014-03-04
申请号：US13037234
申请日：2011-02-28
申请人： William E. Allaire , Bradley L. Taylor , Ting Lu , Sandeep Dutta , Patrick J. Crotty , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
发明人： William E. Allaire , Bradley L. Taylor , Ting Lu , Sandeep Dutta , Patrick J. Crotty , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
IPC分类号： G06F13/00 , G06F12/00 , G06F13/24 , G06F1/00 , H03K19/173
CPC分类号： G06F13/10 , G06F1/26 , G06F1/3287 , G06F15/7867 , G06F15/7871 , Y02D10/171
摘要： An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.
摘要翻译：集成电路可以包括被配置为执行程序代码的处理器系统。处理器系统可以是硬连线的并且包括处理器硬件资源。 IC还可以包括可配置为实现不同物理电路的可编程电路。可编程电路可以耦合到处理器系统。可编程电路可以被配置为共享处理器系统的处理器硬件资源的使用。处理器系统还可以控制诸如上电和/或关断的可编程电路的方面，并且还可以配置可编程电路以在其中实现一个或多个不同的物理电路。

2. 发明申请

US20120185719A1 POWER MANAGEMENT WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中的电源管理
公开(公告)号：US20120185719A1
公开(公告)日：2012-07-19
申请号：US13005994
申请日：2011-01-13
申请人： Bradley L. Taylor , Ting Lu , William E. Allaire , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
发明人： Bradley L. Taylor , Ting Lu , William E. Allaire , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
IPC分类号： G06F1/32
CPC分类号： H03K19/0016 , H03K19/177
摘要： An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.
摘要翻译：集成电路可以包括被配置为执行程序代码的处理器系统，其中处理器系统是硬连线的。 IC还可以包括可配置以实现不同物理电路的可编程电路。可编程电路可以耦合到处理器系统，并且可以被配置为在处理器系统的控制下实现断电过程。

3. 发明授权

US5828231A High voltage tolerant input/output circuit 失效
标题翻译：高耐压输入/输出电路
公开(公告)号：US5828231A
公开(公告)日：1998-10-27
申请号：US700247
申请日：1996-08-20
申请人： Hassan K. Bazargan
发明人： Hassan K. Bazargan
IPC分类号： H03K19/003 , H03K19/185
CPC分类号： H03K19/00315
摘要： A low voltage driver circuit capable of interfacing with a high voltage node. The high voltage tolerant input/output circuit of the present invention has a first stage operating at a low voltage integrated circuit standard and a second stage capable of operating at both the low voltage and a high voltage integrated circuit standard. The second stage operates at high voltage during the tristate mode and at low voltage during an active mode. The second stage uses an output driver having a p-type pull-up transistor coupled to an input/output pad. The input/output pad interfaces with a high voltage or mixed voltage network. An isolator circuit is coupled between the first stage and the second stage for voltage isolation when the second stage is operating at high voltage. A charger circuit maintains the high voltage on a gate of the p-type pull-up transistor during the tristate mode and the low voltage during the active mode. The charger also decreases the voltage on the gate of the p-type pull-up transistor in advance of a transition from the tristate to the active mode. The p-type transistors in the circuit which are exposed to the high voltage have their NWELLs coupled to the high voltage. This configuration prevents the back flow of current from the high voltage network to the second stage and protects the p-type transistors in the circuit from latch up.
摘要翻译：一种能够与高压节点接口的低电压驱动电路。本发明的高耐压输入/输出电路具有在低电压集成电路标准下工作的第一级和能够在低电压和高压集成电路标准下工作的第二级。在三态模式下，第二级工作在高电压，而在主动模式下工作在低电压。第二级使用具有耦合到输入/输出焊盘的p型上拉晶体管的输出驱动器。输入/输出焊盘与高压或混合电压网络接口。当第二级在高电压下工作时，隔离电路耦合在第一级和第二级之间进行电压隔离。充电器电路在三态模式期间保持p型上拉晶体管的栅极上的高电压，并且在活动模式期间保持低电压。在从三态转换到激活模式之前，充电器还降低p型上拉晶体管的栅极上的电压。暴露于高电压的电路中的p型晶体管的NWELL耦合到高电压。该配置防止电流从高电压网络回流到第二级，并且保护电路中的p型晶体管不被锁存。

4. 发明授权

US06810458B1 Method and circuit for hot swap protection 有权
标题翻译：热插拔保护方法和电路
公开(公告)号：US06810458B1
公开(公告)日：2004-10-26
申请号：US10090257
申请日：2002-03-01
申请人： Hassan K. Bazargan , Jian Tan , Atul V. Ghia , Suresh M. Menon
发明人： Hassan K. Bazargan , Jian Tan , Atul V. Ghia , Suresh M. Menon
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A hot swap protection circuit (40) for an integrated circuit being plugged into a powered-up system includes a first circuit (10) for detecting a hot swap condition, a second circuit (20) coupled to the first circuit for preventing a pn junction diode (52) in a pull-up transistor (32) from going into a forward bias condition, and a third circuit (30) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.
摘要翻译：用于插入加电系统的集成电路的热插拔保护电路（40）包括用于检测热插拔状态的第一电路（10），耦合到第一电路的第二电路（20），用于防止pn结上拉晶体管（32）中的二极管（52）进入正向偏置状态，以及耦合到第一和第二电路的第三电路（30），用于防止在热插拔条件期间上拉晶体管导通。

5. 发明授权

US5933025A Low voltage interface circuit with a high voltage tolerance 失效
标题翻译：具有高电压容差的低压接口电路
公开(公告)号：US5933025A
公开(公告)日：1999-08-03
申请号：US784163
申请日：1997-01-15
申请人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
发明人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.
摘要翻译：具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。本发明的一个实施例包括三态控制电路，数据通路，参考电压电路和隔离电路。接口电路提供高阻抗接收模式。在这种模式下，当接口电路的I / O引脚施加的电压足够大于接口电路电源电压时，隔离电路会将电源与I / O引脚隔离开来。接口电路还保护所有的晶体管从栅极到体积，栅极到源极和漏极到大于指定电压的电压降，例如对于额定3V电源的3.6V，当高达5.5V被外部施加到 I / O引脚。在高阻抗模式下，当I / O引脚的外部施加电压足够低于接口电路电源电压时，隔离电路被驱动到大致接口电路电源电压。在低阻模式下，隔离电路被禁用，数据端子的逻辑电平被传输到I / O引脚。本发明的一个实施例提供从数据终端到I / O引脚的缓冲数据路径。

6. 发明授权

US06300839B1 Frequency controlled system for positive voltage regulation 有权
标题翻译：用于正电压调节的频率控制系统
公开(公告)号：US06300839B1
公开(公告)日：2001-10-09
申请号：US09644286
申请日：2000-08-22
申请人： Hassan K. Bazargan , Farshid Shokouhi
发明人： Hassan K. Bazargan , Farshid Shokouhi
IPC分类号： G05F140
CPC分类号： H02M3/073
摘要： In a charge pump system, the frequency of an oscillator is based on the output signals from a plurality of differential amplifiers. Each differential amplifier receives a different reference voltage as well as a common input voltage derived from the pumped voltage. A predetermined logic signal output by the differential amplifiers modifies, i.e. reduces, an original frequency of the oscillator. In this manner, the charge pump system quickly compensates for any overshoot in the pumped voltage in a manner directly correlated to the magnitude of the pumped voltage. If no differential amplifiers output the predetermined logic signal, then the oscillator generates the original frequency. In this manner, the charge pump system also compensates for any undershoot in the pumped voltage by providing the fastest frequency.
摘要翻译：在电荷泵系统中，振荡器的频率基于来自多个差分放大器的输出信号。每个差分放大器接收不同的参考电压以及从泵浦电压得到的公共输入电压。由差分放大器输出的预定逻辑信号修改振荡器的原始频率，即降低振荡器的原始频率。以这种方式，电荷泵系统以与泵送电压的大小直接相关的方式快速补偿泵浦电压中的任何过冲。如果没有差分放大器输出预定的逻辑信号，则振荡器产生原始频率。以这种方式，电荷泵系统还通过提供最快的频率来补偿泵浦电压中的任何下冲。

7. 发明授权

US08612789B2 Power management within an integrated circuit 有权
标题翻译：集成电路内的电源管理
公开(公告)号：US08612789B2
公开(公告)日：2013-12-17
申请号：US13005994
申请日：2011-01-13
申请人： Bradley L. Taylor , Ting Lu , William E. Allaire , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
发明人： Bradley L. Taylor , Ting Lu , William E. Allaire , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
IPC分类号： G06F1/26
CPC分类号： H03K19/0016 , H03K19/177
摘要： An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.
摘要翻译：集成电路可以包括被配置为执行程序代码的处理器系统，其中处理器系统是硬连线的。 IC还可以包括可配置以实现不同物理电路的可编程电路。可编程电路可以耦合到处理器系统，并且可以被配置为在处理器系统的控制下实现断电过程。

8. 发明申请

US20120221833A1 INTEGRATED CIRCUIT WITH PROGRAMMABLE CIRCUITRY AND AN EMBEDDED PROCESSOR SYSTEM 有权
标题翻译：集成电路与可编程电路和嵌入式处理器系统
公开(公告)号：US20120221833A1
公开(公告)日：2012-08-30
申请号：US13037234
申请日：2011-02-28
申请人： William E. Allaire , Bradley L. Taylor , Ting Lu , Sandeep Dutta , Patrick J. Crotty , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
发明人： William E. Allaire , Bradley L. Taylor , Ting Lu , Sandeep Dutta , Patrick J. Crotty , Hassan K. Bazargan , Hy V. Nguyen , Shashank Bhonge
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/10 , G06F1/26 , G06F1/3287 , G06F15/7867 , G06F15/7871 , Y02D10/171
摘要： An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.
摘要翻译：集成电路可以包括被配置为执行程序代码的处理器系统。处理器系统可以是硬连线的并且包括处理器硬件资源。 IC还可以包括可配置为实现不同物理电路的可编程电路。可编程电路可以耦合到处理器系统。可编程电路可以被配置为共享处理器系统的处理器硬件资源的使用。处理器系统还可以控制诸如上电和/或关断的可编程电路的方面，并且还可以配置可编程电路以在其中实现一个或多个不同的物理电路。

9. 发明授权

US07235412B1 Semiconductor component having test pads and method and apparatus for testing same 有权
公开(公告)号：US07235412B1
公开(公告)日：2007-06-26
申请号：US10842770
申请日：2004-05-11
申请人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
发明人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
IPC分类号： H01L21/66
CPC分类号： H01L22/32 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/05567 , H01L2224/05599 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K1/0268 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

10. 发明授权

US07737439B2 Semiconductor component having test pads and method and apparatus for testing same 有权
标题翻译：具有测试焊盘的半导体部件及其测试方法和装置
公开(公告)号：US07737439B2
公开(公告)日：2010-06-15
申请号：US11804391
申请日：2007-05-17
申请人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
发明人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
IPC分类号： H01L23/485
CPC分类号： H01L22/32 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/05567 , H01L2224/05599 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K1/0268 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.
摘要翻译：描述了具有测试焊盘的半导体部件及其测试方法和装置。在一个示例中，获得具有被配置为支撑凸起的触点和多个测试焊盘的接合焊盘图案的未凸起的衬底。多个测试焊盘中的每一个与相应的一个接合焊盘电连通。使用多个测试垫测试衬底。在另一示例中，制造具有被配置为支撑凸起的触点和多个测试焊盘的接合焊盘图案的衬底。多个测试焊盘中的每一个与相应的一个接合焊盘电连通。使用多个测试垫测试衬底。绝缘层形成在多个测试焊盘上。

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