专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07305594B2 Integrated circuit in a maximum input/output configuration 有权
标题翻译：集成电路在最大输入/输出配置
公开(公告)号：US07305594B2
公开(公告)日：2007-12-04
申请号：US10303179
申请日：2002-11-25
申请人： James J. Dietz , David SuitWai Ma
发明人： James J. Dietz , David SuitWai Ma
IPC分类号： G11C29/30 , G11C29/40
CPC分类号： G11C29/1201 , G11C29/48
摘要： A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.
摘要翻译：存储器包括输入/输出路径和电引线。每个输入/输出路径被耦合到单独的电引线。存储器被配置为在测试架构和操作架构中操作。在测试架构中，逻辑允许最大数量的输入/输出路径。在操作架构中，内存使能相同或更少的输入/输出路径。选择配置的方法包括建立操作和测试体系结构，并以更大的输入/输出配置测试存储器。

2. 发明授权

US06702589B1 Leadless socket for decapped semiconductor device 失效
标题翻译：无引线插座，用于封装的半导体器件
公开(公告)号：US06702589B1
公开(公告)日：2004-03-09
申请号：US10222693
申请日：2002-08-16
申请人： David SuitWai Ma , Bing Ren , James J. Dietz
发明人： David SuitWai Ma , Bing Ren , James J. Dietz
IPC分类号： H01R909
CPC分类号： G11C5/04 , G01R1/0433 , H01R4/38 , H01R12/57 , Y10S439/912
摘要： An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.
摘要翻译：公开了一种用于将半导体器件安装到用于测试的电路板的装置。半导体器件包括半导体电路和引线将半导体电路连接到电路板。另外，半导体器件被分解，使得半导体电路的至少一部分被暴露。该装置包括框架和紧固件。框架适于与半导体器件配合，并形成用于访问半导体电路的开口和用于接收半导体器件的边缘表面。紧固件与框架连接，用于将框架可拆卸地连接到电路板。通过使用框架而不是插座，一旦将器件安装到电路板，特别是半导体器件的顶侧，则可以减小到半导体器件的距离，使得可以使用探针来测试器件。

3. 发明授权

US07449909B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07449909B2
公开(公告)日：2008-11-11
申请号：US11707408
申请日：2007-02-16
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

4. 发明授权

US07242208B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07242208B2
公开(公告)日：2007-07-10
申请号：US11386512
申请日：2006-03-22
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

5. 发明授权

US07119567B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07119567B2
公开(公告)日：2006-10-10
申请号：US10243544
申请日：2002-09-12
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/02
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

6. 发明授权

US07643956B2 Continuous self-calibration of internal analog signals 有权
标题翻译：内部模拟信号的连续自校准
公开(公告)号：US07643956B2
公开(公告)日：2010-01-05
申请号：US11649047
申请日：2007-01-03
申请人： David SuitWai Ma
发明人： David SuitWai Ma
IPC分类号： G01R35/00 , G06F11/00
CPC分类号： G06F1/28 , G06F1/26
摘要： A method and apparatus for monitoring and adjusting an analog signal of an operating circuit. The apparatus includes a control circuit, an analog-to-digital converter, and a comparator. The control circuit has an analog generator for generating the analog signal and an adjusting circuit for adjusting the strength of the analog signal. The analog-to-digital converter receives the analog signal and converts the analog signal to a digital signal. The comparator then compares the value of the digital signal to a predetermined value and generates a comparator signal. The adjusting circuit then receives the comparator signal and adjusts the strength of the analog signal based upon the value of the comparator signal. The method includes generating the analog signal, converting the analog signal to a digital signal, comparing the value of the digital signal to a predetermined value and adjusting the strength of the analog signal.
摘要翻译：一种用于监测和调整操作电路的模拟信号的方法和装置。该装置包括一个控制电路，一个模拟 - 数字转换器和一个比较器。控制电路具有用于产生模拟信号的模拟发生器和用于调整模拟信号的强度的调整电路。模拟数字转换器接收模拟信号并将模拟信号转换为数字信号。比较器然后将数字信号的值与预定值进行比较，并产生比较器信号。然后，调节电路接收比较器信号，并根据比较器信号的值调整模拟信号的强度。该方法包括产生模拟信号，将模拟信号转换为数字信号，将数字信号的值与预定值进行比较并调整模拟信号的强度。

7. 发明授权

US06721180B2 Cooling hood for circuit board 有权
标题翻译：电路板冷却罩
公开(公告)号：US06721180B2
公开(公告)日：2004-04-13
申请号：US10209025
申请日：2002-07-31
申请人： Thoai-Thai Le , Guenter Gerstmeier , David SuitWai Ma , Tao Wang
发明人： Thoai-Thai Le , Guenter Gerstmeier , David SuitWai Ma , Tao Wang
IPC分类号： H05K720
CPC分类号： H05K7/20727
摘要： A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.
摘要翻译：提供了一种用于电路板的冷却罩。电路板包括至少一个半导体器件。冷却罩包括安装在电路板上并围绕半导体器件的至少一部分的管道。导管形成入口和出口。冷却介质通过入口进入管道，并通过出口离开管道。

8. 发明授权

US07539075B2 Implementation of a fusing scheme to allow internal voltage trimming 失效
标题翻译：实现融合方案，允许内部电压修整
公开(公告)号：US07539075B2
公开(公告)日：2009-05-26
申请号：US11860332
申请日：2007-09-24
申请人： Jennifer Faye Huckaby , George William Alexander , Steven Michael Baker , David SuitWai Ma
发明人： Jennifer Faye Huckaby , George William Alexander , Steven Michael Baker , David SuitWai Ma
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/20 , G11C29/021 , G11C29/028
摘要： Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.
摘要翻译：提供了用于调整集成电路器件的内部产生的电压的调整设置的方法和装置。在一个实施例中，设备接收内部产生的电压的目标数字值，并将目标数字值与内部产生的电压的当前数字值进行比较。如果比较表明目标数字值与当前数字值之间的差异大于允许阈值，则根据该差异来调整用于修整内部产生的电压的修整设置。可以调节修整设置，直到目标数字值与当前数字值之间的差小于或等于允许阈值。

9. 发明授权

US07277350B2 Implementation of a fusing scheme to allow internal voltage trimming 有权
标题翻译：实现融合方案，允许内部电压修整
公开(公告)号：US07277350B2
公开(公告)日：2007-10-02
申请号：US11142023
申请日：2005-06-01
申请人： Jennifer Faye Huckaby , George William Alexander , Steven Michael Baker , David SuitWai Ma
发明人： Jennifer Faye Huckaby , George William Alexander , Steven Michael Baker , David SuitWai Ma
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/20 , G11C29/021 , G11C29/028
摘要： Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.
摘要翻译：提供了用于调整集成电路器件的内部产生的电压的调整设置的方法和装置。在一个实施例中，设备接收内部产生的电压的目标数字值，并将目标数字值与内部产生的电压的当前数字值进行比较。如果比较表明目标数字值与当前数字值之间的差异大于允许阈值，则根据该差异来调整用于修整内部产生的电压的修整设置。可以调节修整设置，直到目标数字值与当前数字值之间的差小于或等于允许阈值。

10. 发明授权

US07177373B2 Continuous self-calibration of internal analog signals 有权
标题翻译：内部模拟信号的连续自校准
公开(公告)号：US07177373B2
公开(公告)日：2007-02-13
申请号：US10216012
申请日：2002-08-09
申请人： David SuitWai Ma
发明人： David SuitWai Ma
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： G06F1/28 , G06F1/26
摘要： A method and apparatus for monitoring and adjusting an analog signal of an operating circuit. The apparatus includes a control circuit, an analog-to-digital converter, and a comparator. The control circuit has an analog generator for generating the analog signal and an adjusting circuit for adjusting the strength of the analog signal. The analog-to-digital converter receives the analog signal and converts the analog signal to a digital signal. The comparator then compares the value of the digital signal to a predetermined value and generates a comparator signal. The adjusting circuit then receives the comparator signal and adjusts the strength of the analog signal based upon the value of the comparator signal. The method includes generating the analog signal, converting the analog signal to a digital signal, comparing the value of the digital signal to a predetermined value and adjusting the strength of the analog signal.
摘要翻译：一种用于监测和调整操作电路的模拟信号的方法和装置。该装置包括一个控制电路，一个模拟 - 数字转换器和一个比较器。控制电路具有用于产生模拟信号的模拟发生器和用于调整模拟信号的强度的调整电路。模拟数字转换器接收模拟信号并将模拟信号转换为数字信号。比较器然后将数字信号的值与预定值进行比较，并产生比较器信号。然后，调节电路接收比较器信号，并根据比较器信号的值调整模拟信号的强度。该方法包括产生模拟信号，将模拟信号转换为数字信号，将数字信号的值与预定值进行比较，并调整模拟信号的强度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式