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1. 发明授权

US06721180B2 Cooling hood for circuit board 有权
标题翻译：电路板冷却罩
公开(公告)号：US06721180B2
公开(公告)日：2004-04-13
申请号：US10209025
申请日：2002-07-31
申请人： Thoai-Thai Le , Guenter Gerstmeier , David SuitWai Ma , Tao Wang
发明人： Thoai-Thai Le , Guenter Gerstmeier , David SuitWai Ma , Tao Wang
IPC分类号： H05K720
CPC分类号： H05K7/20727
摘要： A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.
摘要翻译：提供了一种用于电路板的冷却罩。电路板包括至少一个半导体器件。冷却罩包括安装在电路板上并围绕半导体器件的至少一部分的管道。导管形成入口和出口。冷却介质通过入口进入管道，并通过出口离开管道。

2. 发明授权

US06946889B2 Self alignment system for complement clocks 失效
标题翻译：补码时钟自对准系统
公开(公告)号：US06946889B2
公开(公告)日：2005-09-20
申请号：US10364716
申请日：2003-02-11
申请人： Thoai-Thai Le , George Alexander , Guenter Gerstmeier
发明人： Thoai-Thai Le , George Alexander , Guenter Gerstmeier
IPC分类号： G01D18/00 , G06F1/04 , G06F1/12 , H03K5/06 , H03K5/151 , H03K5/153
CPC分类号： H03K5/151 , G06F1/12
摘要： A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.
摘要翻译：用于补码时钟信号的自对准系统包括第一延迟电路和第二延迟电路。第一时钟信号可以通过第一延迟电路传播，并且第二时钟信号可以通过第二延迟电路传播。可以根据第一和第二时钟信号来选择性地改变第一和第二延迟电路中的每一个的传播延迟。

3. 发明授权

US06891404B2 Auto-adjustment of self-refresh frequency 失效
标题翻译：自动调整自刷新频率
公开(公告)号：US06891404B2
公开(公告)日：2005-05-10
申请号：US10166837
申请日：2002-06-11
申请人： Thoai-Thai Le , Juergen Lindolf , Guenter Gerstmeier
发明人： Thoai-Thai Le , Juergen Lindolf , Guenter Gerstmeier
IPC分类号： G11C11/406 , G11C29/02 , H03L7/00 , H03K9/06
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2211/4061 , H03L7/00
摘要： A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.
摘要翻译：一种调整控制信号的方法，包括以未知频率生成控制信号，并根据未知频率自动调节控制信号的未知频率。

4. 发明授权

US06756655B2 Fuse for a semiconductor configuration and method for its production 失效
标题翻译：用于半导体配置的保险丝及其生产方法
公开(公告)号：US06756655B2
公开(公告)日：2004-06-29
申请号：US10013298
申请日：2001-12-10
申请人： Thoai-Thai Le , Jürgen Lindolf
发明人： Thoai-Thai Le , Jürgen Lindolf
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.
摘要翻译：描述了一种半导体结构，其包括具有设置在半导体主体的主表面上的主表面和绝缘体层的半导体本体。绝缘体层具有形成在其中的空腔，其延伸到半导体本体的主表面。具有可熔部分的保险丝从半导体本体的主表面朝着与半导体主体的主表面成直角的绝缘体层的上表面延伸，并且保险丝嵌入在腔中。还描述了具有熔丝的半导体结构的制造方法。

5. 发明授权

US06970395B2 Memory device and method of reading data from a memory device 失效
标题翻译：从存储器件读取数据的存储器件和方法
公开(公告)号：US06970395B2
公开(公告)日：2005-11-29
申请号：US10658130
申请日：2003-09-08
申请人： Thoai-Thai Le , Ralf Klein , Eckhard Brass , George Alexander
发明人： Thoai-Thai Le , Ralf Klein , Eckhard Brass , George Alexander
IPC分类号： G11C7/10 , G11C11/4076 , G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C2207/2281
摘要： A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.
摘要翻译：存储器件包括具有延迟元件的延迟锁定环路电路和耦合到延迟锁定环路电路的同步电路。同步电路接收同步使能信号并输出多个使能信号，包括耦合到输出电路的使能信号。由于使能信号与读取信号同步，所以可以提供更多的时间将数据读入缓冲器。从存储器件读取数据的方法将同步使能信号和外部时钟信号耦合到同步电路。基于外部时钟信号的同步使能信号和延迟的时钟信号，产生读取信号和输出使能。由于输出信号与读取信号同步，所以允许感应功能更多的时间。

6. 发明授权

US06389086B1 Digital circuit having a filter unit for suppressing glitches 有权
标题翻译：具有用于抑制毛刺的滤波器单元的数字电路
公开(公告)号：US06389086B1
公开(公告)日：2002-05-14
申请号：US09521396
申请日：2000-03-08
申请人： Thoai-Thai Le , Eckhard Brass , Markus Biebl
发明人： Thoai-Thai Le , Eckhard Brass , Markus Biebl
IPC分类号： H03B110
CPC分类号： H03K5/1252
摘要： A digital circuit has a signal input terminal and a signal output terminal. The digital circuit additionally has a logic circuit unit, whose input is connected to the signal input terminal and whose output is connected to the signal output terminal via a switching element. Furthermore, it has a filter unit, whose input is connected to the signal input terminal and whose output is connected to a control input of the switching element. The filter unit serves for suppressing glitches on a digital signal present at its input.
摘要翻译：数字电路具有信号输入端和信号输出端。数字电路还具有逻辑电路单元，其输入端连接到信号输入端子，其输出端经由开关元件连接到信号输出端子。此外，它具有滤波器单元，其输入端连接到信号输入端，并且其输出端连接到开关元件的控制输入端。滤波器单元用于抑制存在于其输入端的数字信号的毛刺。

7. 发明授权

US06838917B2 Circuit configuration for processing data, and method for identifying an operating state 有权
标题翻译：用于处理数据的电路配置，以及用于识别操作状态的方法
公开(公告)号：US06838917B2
公开(公告)日：2005-01-04
申请号：US10266354
申请日：2002-10-07
申请人： Eckhard Brass , Bernd Klehn , Ralf Klein , Thoai-Thai Le
发明人： Eckhard Brass , Bernd Klehn , Ralf Klein , Thoai-Thai Le
IPC分类号： G11C7/10 , G11C7/22 , H03L7/06
CPC分类号： G11C7/1066 , G11C7/04 , G11C7/1072 , G11C7/22 , G11C7/222
摘要： A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.
摘要翻译：用于处理数据的电路配置，特别是半导体存储器芯片，具有用于设置两个信号之间的相位或频率关系的控制电路。数字计数器检测两个信号之间的相位或频率差，并且计数器读数用于调节相位或频率关系。试验表明，计数器读数表示电路配置中的工作状态，因此表示用于评估电路配置工作状态的简单信号。优选地，计数器读数作为调整电路配置中时间关键或性能关键电路部件的速度或功率的基础，从而获得具有中间切换速度的操作状态。

8. 发明授权

US06717447B1 Delay adjustment circuit 有权
标题翻译：延时调节电路
公开(公告)号：US06717447B1
公开(公告)日：2004-04-06
申请号：US10271955
申请日：2002-10-15
申请人： Thoai-Thai Le , Ralf Klein
发明人： Thoai-Thai Le , Ralf Klein
IPC分类号： H03L700
CPC分类号： H03L7/0814 , H03K2005/00058 , H03K2005/00234
摘要： A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.
摘要翻译：一种延迟调整电路，用于减少来自半导体内部时钟的系统时钟和反馈时钟之间的相移。电路包括差分脉冲发生器，当反馈时钟引导系统时钟时，差分脉冲发生器提供与反馈时钟180度异相的中间时钟，否则等于反馈时钟。差分脉冲发生器还提供在一段时间内处于逻辑高的差分脉冲信号，通过该时间段，系统时钟和中间时钟的反相相移。该电路还包括一个延迟控制单元和延迟单元，该延迟单元将临时时钟延迟一段时间。所产生的与系统时钟相差180度的延迟中间时钟被反相，以提供与系统时钟同相的内部时钟。

9. 发明授权

US06717200B1 Vertical field effect transistor with internal annular gate and method of production 有权
标题翻译：具有内部环形栅极的垂直场效应晶体管及其制造方法
公开(公告)号：US06717200B1
公开(公告)日：2004-04-06
申请号：US09408688
申请日：1999-09-30
申请人： Florian Schamberger , Helmut Schneider , Jürgen Lindolf , Thoai-Thai Le
发明人： Florian Schamberger , Helmut Schneider , Jürgen Lindolf , Thoai-Thai Le
IPC分类号： H01L31119
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/42368 , H01L29/7827
摘要： A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.
摘要翻译：垂直MOS场效应晶体管包括设置在沟槽中的栅极，沟道以及设置在沟槽壁上的衬底中的源极和漏极。栅极环形地围绕从衬底表面延伸到漏极设置在沟槽底部的漏极端子。通过在制造栅极时采用倾斜注入，可以在具有不同宽度的沟槽的衬底上制造具有不同沟道长度的垂直晶体管。还提供了一种制造垂直场效应晶体管的方法。

10. 发明授权

US06642804B2 Oscillator circuit 有权
标题翻译：振荡电路
公开(公告)号：US06642804B2
公开(公告)日：2003-11-04
申请号：US10074578
申请日：2002-02-13
申请人： Ioannis Chrissostomidis , Thoai-Thai Le
发明人： Ioannis Chrissostomidis , Thoai-Thai Le
IPC分类号： H03L700
CPC分类号： H03K3/0231 , H03K3/011
摘要： The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C′) which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C′) which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C′) can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.
摘要翻译：本发明创建了一种振荡器电路，特别是用于动态半导体存储器的刷新定时器装置，其具有连接在第一节点（6）和第一电源电位（P2）之间的电容器装置（C; C'）; 用于为经由第一晶体管器件（T4）连接到第一节点（6）并且具有电流源（SQ）的电容器器件（C; C'）提供充电电流的电流镜电路（T1; T2）），用于提供基本上温度无关的参考电流（Iref）; 连接在第一节点（6）和第一电源电位（P2）之间的第二晶体管器件（T5）; 第一和第二晶体管器件（T4; T5）和控制信号被配置成使得当第一和第二晶体管器件（T4; T5）的电位（V comp）节点（6）低于参考电位（Vref），并且当第一节点（6）处的电位（Vcomp）高于参考电位（Vref）时，可以经由第一节点（6）放电，输出（A）的信号振荡。

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