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1. 发明授权

US07971034B2 Reduced overhead address mode change management in a pipelined, recycling microprocessor 失效
标题翻译：在流水线回收微处理器中减少开销地址模式更改管理
公开(公告)号：US07971034B2
公开(公告)日：2011-06-28
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

2. 发明申请

US20090240929A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR 失效
标题翻译：方法，系统和计算机程序产品，用于在管道，回收微处理器中减少地址模式更改管理
公开(公告)号：US20090240929A1
公开(公告)日：2009-09-24
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

3. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

4. 发明申请

US20090210656A1 METHOD AND SYSTEM FOR OVERLAPPING EXECUTION OF INSTRUCTIONS THROUGH NON-UNIFORM EXECUTION PIPELINES IN AN IN-ORDER PROCESSOR 失效
标题翻译：通过非订单执行管理员在订单处理程序中执行指令的方法和系统
公开(公告)号：US20090210656A1
公开(公告)日：2009-08-20
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F15/76 , G06F9/02 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

5. 发明授权

US07921279B2 Operand and result forwarding between differently sized operands in a superscalar processor 失效
标题翻译：操作数和结果在超标量处理器中的不同大小的操作数之间转发
公开(公告)号：US07921279B2
公开(公告)日：2011-04-05
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

6. 发明授权

US07913067B2 Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor 失效
标题翻译：用于通过按顺序处理器中的非均匀执行流水线重复执行指令的方法和系统
公开(公告)号：US07913067B2
公开(公告)日：2011-03-22
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

7. 发明授权

US07861064B2 Method, system, and computer program product for selectively accelerating early instruction processing 失效
标题翻译：方法，系统和计算机程序产品，用于选择性加速早期指令处理
公开(公告)号：US07861064B2
公开(公告)日：2010-12-28
申请号：US12037861
申请日：2008-02-26
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
IPC分类号： G06F9/34 , G06F9/38
CPC分类号： G06F9/3826 , G06F9/3836
摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.
摘要翻译：一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据由于你而不被推迟处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。相应的系统和计算机程序产品。

8. 发明授权

US07490121B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07490121B2
公开(公告)日：2009-02-10
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

9. 发明授权

US07853635B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07853635B2
公开(公告)日：2010-12-14
申请号：US11749224
申请日：2007-05-16
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.
摘要翻译：超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

10. 发明授权

US07266580B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07266580B2
公开(公告)日：2007-09-04
申请号：US10435976
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.
摘要翻译：本文中讨论了用于对具有各种长度的有符号和无符号操作数进行二进制乘法的方法和装置。这是一个概念，可以分为两部分，第一部分是乘法硬件本身，紧凑型，小于满量程的乘法器，在乘数上使用Booth或其他类型的重新编码方法，以减少每个部分产品的数量扫描和实现，使得具有大操作数的乘法运算可以被分解成适合于该中型乘法器的操作子组，其结果（这里称为模块化产品）可以针织在一起以形成正确的，完成品。该概念的第二部分是用于将操作数分成子组并将数据和控制信号输入到乘法器的支持硬件，以及用于对准和组合模块化产品以获得最终产品的算法和装置。用于获得由操作指定的结果的这些算法可以与可以使用乘法器的支持硬件一样变化，使得该乘法器是非常灵活和强大的设计。

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