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1. 发明授权

US5936444A Zero power power-on reset circuit 失效
标题翻译：零电源上电复位电路
公开(公告)号：US5936444A
公开(公告)日：1999-08-10
申请号：US977779
申请日：1997-11-25
申请人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.
摘要翻译：上电复位电路包括用于在加电期间建立电荷的第一充电阶段。感测第一充电阶段的上升电压并用于控制用于对第二充电阶段充电的装置。当第二充电阶段达到第一电压电平时，电路跳闸以将第一至第二电荷的电位拉到地。第一充电阶段的接地被反馈到充电装置，其关闭其功率燃烧部件并在第二充电阶段保持第一电压电平。

2. 发明授权

US5963496A Sense amplifier with zero power idle mode 失效
标题翻译：具有零功率空闲模式的感应放大器
公开(公告)号：US5963496A
公开(公告)日：1999-10-05
申请号：US64811
申请日：1998-04-22
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/06 , G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C7/1036
摘要： A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
摘要翻译：用于串行配置存储器的读出放大器包括响应于控制脉冲以控制器方式启用和禁用的多个级。在外部提供的时钟信号的每第N个周期产生控制脉冲，该时钟用于计时表示存储器件的内容的比特流。在优选实施例中，N个这样的感测放大器用于并行地读出构成访问的存储器位置的N个存储器单元（位）。因此，感测放大器仅在足以读出存储器单元的一段时间内是有效的。

3. 发明授权

US5946267A Zero power high speed configuration memory 失效
标题翻译：零功率高速配置存储器
公开(公告)号：US5946267A
公开(公告)日：1999-08-31
申请号：US978286
申请日：1997-11-25
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/02 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
摘要翻译：串行配置存储器件包括以流水线方式执行读出数据和输出比特流的架构。结果，该装置能够仅基于外部提供的时钟的频率输出比特流，并且不受感测放大器电路的较慢的操作速度的限制。提供了一种缓存方案，其允许在复位周期期间预加载第一字节，使得一旦复位周期完成，设备就可以立即开始输出比特流。在本发明的优选实施例中，比特流由从存储器位置零开始的串行访问的存储器位置组成。在一个变型中，比特流可以从除存储器位置零之外的存储器位置开始。

4. 发明授权

US5493244A Breakdown protection circuit using high voltage detection 失效
标题翻译：击穿保护电路采用高压检测
公开(公告)号：US5493244A
公开(公告)日：1996-02-20
申请号：US180689
申请日：1994-01-13
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale
IPC分类号： H03K17/0814 , H03K17/10 , H03K17/687 , H03K17/693 , H03K19/003 , H03K5/08
CPC分类号： H03K17/693 , H03K17/08142 , H03K17/102 , H03K19/00315 , H03K19/00361 , H01L2924/0002
摘要： A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states. When the control transistor is in an off state and the protection transistor is in a protecting condition, the voltage drop along the controlled path will cause the protection transistor to turn off, so as to limit the voltage across the control transistor. A second controlled path is preferably in series connection with the first controlled path. The second controlled path includes n-channel transistors, with one of the transistors fixed at V.sub.cc in order to guard against gate-aided junction breakdown of the other transistor. In this embodiment, the high voltage circuit is preferably an inverter circuit.
摘要翻译：高压电路包括用于将高电压（Vpp）和低电压（Vcc）中的一个提供给包括控制p沟道晶体管和保护p沟道晶体管的串联连接的受控路径的第一开关器件。利用高电压检测器来确定是否将Vpp或Vcc应用于受控路径。高电压检测器还在Vpp操作期间为保护p沟道晶体管建立了保护条件。另一方面，检测器在Vcc操作期间建立非保护状态，从而使得保护p沟道晶体管对电路性能是透明的。信号输入在控制p沟道晶体管的导通和截止状态之间切换。当控制晶体管处于断开状态并且保护晶体管处于保护状态时，沿受控路径的电压降将导致保护晶体管截止，从而限制控制晶体管两端的电压。第二受控路径优选地与第一受控路径串联连接。第二受控路径包括n沟道晶体管，其中一个晶体管固定在Vcc，以防止另一个晶体管的栅极辅助结击穿。在本实施例中，高压电路优选为逆变器电路。

5. 发明授权

US6140993A Circuit for transferring high voltage video signal without signal loss 失效
标题翻译：用于传输高电压视频信号的电路，无信号丢失
公开(公告)号：US6140993A
公开(公告)日：2000-10-31
申请号：US97866
申请日：1998-06-16
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2300/0876 , G09G2310/0289 , G09G3/2011 , G09G3/2074
摘要： A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
摘要翻译：用于传送高压模拟视频信号同时能够使用常规低电压逻辑电平的电路包括由高电压电源供电的第一晶体管，以在高电压电平下偏置传输晶体管。传输晶体管接收高电压视频信号，并且由于高电压偏压能够通过视频信号而不会由于馈通效应而导致信号衰减，从而保持视频信号的保真度。第二晶体管提供接地电位，其操作以关闭传输晶体管，从而禁止视频信号通过其传输。可操作地耦合到第一晶体管的第三晶体管操作以在第二晶体管工作时关断第一晶体管。

6. 发明授权

US6115305A Method and apparatus for testing a video display chip 有权
标题翻译：用于测试视频显示芯片的方法和装置
公开(公告)号：US6115305A
公开(公告)日：2000-09-05
申请号：US333805
申请日：1999-06-15
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G01R31/02 , G01R31/3185 , G09G3/20 , G11C29/02 , G11C29/10 , G11C29/34 , G11C7/00
CPC分类号： G11C29/02 , G01R31/31855
摘要： A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
摘要翻译：视频芯片包括用于检测开路和短路的测试电路。该电路包括串联连接的晶体管链和测试寄存器。列线和行线都有一个电路。位模式被驱动到列或行线上并被接收在相应的测试电路中。该模式被读出并与输入模式进行比较以检测故障线路。

7. 发明授权

US5473500A Electrostatic discharge circuit for high speed, high voltage circuitry 失效
标题翻译：用于高速，高压电路的静电放电电路
公开(公告)号：US5473500A
公开(公告)日：1995-12-05
申请号：US180673
申请日：1994-01-13
申请人： James E. Payne , Saroj Pathak , Glen A. Rosendale
发明人： James E. Payne , Saroj Pathak , Glen A. Rosendale
IPC分类号： H01L27/088 , H01L21/8234 , H02H7/20 , H02H9/04 , H03K19/003 , H04B15/00 , H02H3/22
CPC分类号： H03K19/00315 , H02H9/046
摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via a transistor and inverter.
摘要翻译：保护电路包括用于放大在信号节点处引入的负ESD脉冲的第一控制路径。第一受控路径经由第一晶体管的源极和漏极从信号节点到Vcc。晶体管的栅极通过栅极通过电阻和逆变器连接到固定电压电位（Vcc）而处于软接地。第二控制路径通过串联的第二和第三晶体管的源极和漏极区域将正的ESD脉冲放电到地。第二晶体管具有通过电阻器和反相器接地的Vcc连接的栅极。第三个晶体管通过电阻器和逆变器在Vcc处于软接地。第三晶体管被超过第三晶体管的阈值电压的正电压导通，但是第二晶体管通过限制施加到第三晶体管的电压来防止对第三晶体管的损坏。如果低电压电路连接到信号节点，则保护电路可以包括通过第四晶体管的第三受控路径。第四晶体管包括通过晶体管和反相器将栅极连接到地而被连接的栅极。

8. 发明授权

US5383193A Method for testing non-volatile memories 失效
标题翻译：测试非易失性存储器的方法
公开(公告)号：US5383193A
公开(公告)日：1995-01-17
申请号：US951207
申请日：1992-09-25
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne
IPC分类号： G11C29/44 , G11C29/52 , G11C29/00
CPC分类号： G11C29/52 , G11C29/44
摘要： A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications. In suitably equipped memories, the addresses of weak cells can be recorded and redundant cell groups substituted as replacements.
摘要翻译：提供了一种用于测试不需要写入或擦除任何单元并且允许测试所有正常存储器单元的非可编程非易失性存储器的方法。测试发生在器件I / O引脚上，并且在EPROM存储器单元已被批量擦除并放置在不透紫外线的封装内的情况下很有用。非易失性存储器是具有行和列的存储体的类型。每个银行必须具有地址解码器和用于更改银行之间的地址的手段。提供了与非编程状态不同的单独的辅助单元或单元行。为辅助单元提供地址，然后为正常单元提供地址，并测量寻址正常单元之间的间隔和输出信号的出现，并将其与预定的固定限制进行比较。如果超出限制，则该地址被识别为速度不符合产品规格的弱电池的地址。在适当配置的存储器中，可以记录弱电池的地址，并将冗余的电池组替换为替换。

9. 发明授权

US5272674A High speed memory sense amplifier with noise reduction 失效
标题翻译：具有降噪功能的高速存储读出放大器
公开(公告)号：US5272674A
公开(公告)日：1993-12-21
申请号：US948481
申请日：1992-09-21
申请人： Saroj Pathak , Glen A. Rosendale
发明人： Saroj Pathak , Glen A. Rosendale
IPC分类号： G11C17/00 , G11C7/02 , G11C7/06 , G11C7/10 , G11C16/06 , G11C16/26 , G11C7/00
CPC分类号： G11C7/02 , G11C16/26 , G11C7/067 , G11C7/1006
摘要： A read circuit for a semiconductor memory that includes a pass transistor between the output of a first sense amplifier reading the memory and a latch. The pass transistor blocks transmission of the sense amplifier's output to the latch whenever a noise glitch producing condition is sensed. A second sense amplifier connected through the same conductive line to the memory cell array as the first sense amplifier has a faster response and lower current threshold in order to detect the glitch producing condition. A pulse generator receives the output of the second sense amplifier and provides a control signal pulse of predetermined duration following detection of the glitch producing condition by the second sense amplifier. The pulse is received by a control gate of the pass transistor, turning the transistor off during the duration of the pulse.
摘要翻译：一种用于半导体存储器的读取电路，其包括在读取存储器的第一读出放大器的输出端与锁存器之间的传输晶体管。每当检测到噪声毛刺产生条件时，传递晶体管阻止读出放大器的输出到锁存器的传输。通过与第一读出放大器相同的导线连接到存储单元阵列的第二读出放大器具有更快的响应和更低的电流阈值，以便检测毛刺产生状况。脉冲发生器接收第二读出放大器的输出，并在由第二读出放大器检测到毛刺产生状态之后提供预定持续时间的控制信号脉冲。脉冲由传输晶体管的控制栅极接收，在脉冲持续时间内关断晶体管。

10. 发明授权

US06476785B1 Drive circuit for liquid crystal display cell 有权
标题翻译：液晶显示单元的驱动电路
公开(公告)号：US06476785B1
公开(公告)日：2002-11-05
申请号：US09436064
申请日：1999-11-08
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： G05B1942
CPC分类号： G09G3/3659 , G09G2300/0814 , G09G2300/0842 , G09G2300/0852
摘要： A driver circuit for use in an array of picture elements in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor responsive to a first select signal controls the coupling of a first image to a first storage capacitor. A second select switch transistor responsive to a second select signal controls the coupling of a second image to a second storage capacitor. The first storage capacitor may be selectively coupled to an output node by means of a first enable switch transistor responsive to a first enable signal. The second storage capacitor may be selectively coupled to the same output node by means of a second enable switch transistor responsive to a second enable signal. By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.
摘要翻译：用于液晶显示器中的像素阵列的驱动电路能够在接收第二组图像数据的同时显示一组图像数据。响应于第一选择信号的第一选择开关晶体管控制第一图像与第一存储电容器的耦合。响应于第二选择信号的第二选择开关晶体管控制第二图像与第二存储电容器的耦合。可以通过响应于第一使能信号的第一使能开关晶体管将第一存储电容器选择性地耦合到输出节点。第二存储电容器可以通过响应于第二使能信号的第二使能开关晶体管选择性地耦合到相同的输出节点。通过对开关晶体管的适当操作，一个存储电容器可以耦合到输出节点，而另一个存储电容器与输出节点隔离并接收新的图像数据。

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