专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06476785B1 Drive circuit for liquid crystal display cell 有权
标题翻译：液晶显示单元的驱动电路
公开(公告)号：US06476785B1
公开(公告)日：2002-11-05
申请号：US09436064
申请日：1999-11-08
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： G05B1942
CPC分类号： G09G3/3659 , G09G2300/0814 , G09G2300/0842 , G09G2300/0852
摘要： A driver circuit for use in an array of picture elements in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor responsive to a first select signal controls the coupling of a first image to a first storage capacitor. A second select switch transistor responsive to a second select signal controls the coupling of a second image to a second storage capacitor. The first storage capacitor may be selectively coupled to an output node by means of a first enable switch transistor responsive to a first enable signal. The second storage capacitor may be selectively coupled to the same output node by means of a second enable switch transistor responsive to a second enable signal. By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.
摘要翻译：用于液晶显示器中的像素阵列的驱动电路能够在接收第二组图像数据的同时显示一组图像数据。响应于第一选择信号的第一选择开关晶体管控制第一图像与第一存储电容器的耦合。响应于第二选择信号的第二选择开关晶体管控制第二图像与第二存储电容器的耦合。可以通过响应于第一使能信号的第一使能开关晶体管将第一存储电容器选择性地耦合到输出节点。第二存储电容器可以通过响应于第二使能信号的第二使能开关晶体管选择性地耦合到相同的输出节点。通过对开关晶体管的适当操作，一个存储电容器可以耦合到输出节点，而另一个存储电容器与输出节点隔离并接收新的图像数据。

2. 发明授权

US5999038A Fuse circuit having zero power draw for partially blown condition 有权
标题翻译：保险丝电路具有零功率抽吸用于部分吹风状态
公开(公告)号：US5999038A
公开(公告)日：1999-12-07
申请号：US160526
申请日：1998-09-24
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： G11C17/18 , G11C17/16 , G11C29/00 , H01H20060101 , H01H37/76 , H01H85/00 , H01H85/044 , H01H85/46 , H01L21/82 , H01L21/822 , H01L27/00 , H01L27/04 , H03K17/56 , H03K19/003
CPC分类号： G11C17/18
摘要： A fuse circuit includes a fusible element and a feedback path which causes the circuit to behave as if the fusible element is fully blown even though the fusible element in fact is partially intact. While a partially intact fuse normally would result in a continuous drain of power, the feedback path cuts off the current flow through the partially intact fusible element.
摘要翻译：熔丝电路包括可熔元件和反馈路径，其使得电路的行为就好像即使可熔元件实际上是部分完整的，易熔元件完全熔断。虽然部分完整的保险丝通常会导致功率的持续耗尽，但反馈路径切断了通过部分完整的可熔元件的电流。

3. 发明授权

US5936444A Zero power power-on reset circuit 失效
标题翻译：零电源上电复位电路
公开(公告)号：US5936444A
公开(公告)日：1999-08-10
申请号：US977779
申请日：1997-11-25
申请人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.
摘要翻译：上电复位电路包括用于在加电期间建立电荷的第一充电阶段。感测第一充电阶段的上升电压并用于控制用于对第二充电阶段充电的装置。当第二充电阶段达到第一电压电平时，电路跳闸以将第一至第二电荷的电位拉到地。第一充电阶段的接地被反馈到充电装置，其关闭其功率燃烧部件并在第二充电阶段保持第一电压电平。

4. 发明授权

US06618289B2 High voltage bit/column latch for Vcc operation 有权
标题翻译：用于Vcc操作的高电压位/列锁存器
公开(公告)号：US06618289B2
公开(公告)日：2003-09-09
申请号：US10039916
申请日：2001-10-29
申请人： Saroj Pathak , James E. Payne , Harry H. Kuo
发明人： Saroj Pathak , James E. Payne , Harry H. Kuo
IPC分类号： G11C1606
CPC分类号： G11C16/24
摘要： A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.
摘要翻译：一个位/列锁存器，包括一对第一和第二交叉耦合CMOS反相器。该对的每个反相器包括NMOS晶体管和PMOS晶体管。第一个CMOS反相器的NMOS晶体管的源极通过控制晶体管耦合到地，并且其输出连接到相关的位线。当位于相应存储单元上的低电压数据出现在位线上时，控制晶体管几乎不导通，以削弱第一反相器的NMOS晶体管。这使得位线上的数据更容易打开第二反相器的NMOS晶体管，以便将位锁存器从存储“低”切换到存储“高”。换句话说，来自位线的数据位被加载到位锁存器中。此后，控制晶体管被强烈导通，因此对锁存器变得透明。因此，当位线稍后上升到高编程电平时，锁存器是稳定的。

5. 发明授权

US5963496A Sense amplifier with zero power idle mode 失效
标题翻译：具有零功率空闲模式的感应放大器
公开(公告)号：US5963496A
公开(公告)日：1999-10-05
申请号：US64811
申请日：1998-04-22
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/06 , G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C7/1036
摘要： A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
摘要翻译：用于串行配置存储器的读出放大器包括响应于控制脉冲以控制器方式启用和禁用的多个级。在外部提供的时钟信号的每第N个周期产生控制脉冲，该时钟用于计时表示存储器件的内容的比特流。在优选实施例中，N个这样的感测放大器用于并行地读出构成访问的存储器位置的N个存储器单元（位）。因此，感测放大器仅在足以读出存储器单元的一段时间内是有效的。

6. 发明授权

US5946267A Zero power high speed configuration memory 失效
标题翻译：零功率高速配置存储器
公开(公告)号：US5946267A
公开(公告)日：1999-08-31
申请号：US978286
申请日：1997-11-25
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/02 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
摘要翻译：串行配置存储器件包括以流水线方式执行读出数据和输出比特流的架构。结果，该装置能够仅基于外部提供的时钟的频率输出比特流，并且不受感测放大器电路的较慢的操作速度的限制。提供了一种缓存方案，其允许在复位周期期间预加载第一字节，使得一旦复位周期完成，设备就可以立即开始输出比特流。在本发明的优选实施例中，比特流由从存储器位置零开始的串行访问的存储器位置组成。在一个变型中，比特流可以从除存储器位置零之外的存储器位置开始。

7. 发明授权

US5493244A Breakdown protection circuit using high voltage detection 失效
标题翻译：击穿保护电路采用高压检测
公开(公告)号：US5493244A
公开(公告)日：1996-02-20
申请号：US180689
申请日：1994-01-13
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale
IPC分类号： H03K17/0814 , H03K17/10 , H03K17/687 , H03K17/693 , H03K19/003 , H03K5/08
CPC分类号： H03K17/693 , H03K17/08142 , H03K17/102 , H03K19/00315 , H03K19/00361 , H01L2924/0002
摘要： A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states. When the control transistor is in an off state and the protection transistor is in a protecting condition, the voltage drop along the controlled path will cause the protection transistor to turn off, so as to limit the voltage across the control transistor. A second controlled path is preferably in series connection with the first controlled path. The second controlled path includes n-channel transistors, with one of the transistors fixed at V.sub.cc in order to guard against gate-aided junction breakdown of the other transistor. In this embodiment, the high voltage circuit is preferably an inverter circuit.
摘要翻译：高压电路包括用于将高电压（Vpp）和低电压（Vcc）中的一个提供给包括控制p沟道晶体管和保护p沟道晶体管的串联连接的受控路径的第一开关器件。利用高电压检测器来确定是否将Vpp或Vcc应用于受控路径。高电压检测器还在Vpp操作期间为保护p沟道晶体管建立了保护条件。另一方面，检测器在Vcc操作期间建立非保护状态，从而使得保护p沟道晶体管对电路性能是透明的。信号输入在控制p沟道晶体管的导通和截止状态之间切换。当控制晶体管处于断开状态并且保护晶体管处于保护状态时，沿受控路径的电压降将导致保护晶体管截止，从而限制控制晶体管两端的电压。第二受控路径优选地与第一受控路径串联连接。第二受控路径包括n沟道晶体管，其中一个晶体管固定在Vcc，以防止另一个晶体管的栅极辅助结击穿。在本实施例中，高压电路优选为逆变器电路。

8. 发明授权

US06809550B2 High speed zero DC power programmable logic device (PLD) architecture 失效
标题翻译：高速零直流电源可编程逻辑器件（PLD）架构
公开(公告)号：US06809550B2
公开(公告)日：2004-10-26
申请号：US10251402
申请日：2002-09-20
申请人： Saroj Pathak , James E. Payne , Victor V. Nguyen , Harry H. Kuo
发明人： Saroj Pathak , James E. Payne , Victor V. Nguyen , Harry H. Kuo
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G11C16/0433 , G11C16/26 , H03K19/17704 , H03K19/17728 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.
摘要翻译：可编程逻辑器件（PLD）架构包括多个PLD单位逻辑单元。每个单个位逻辑单元由包括可编程单元单元，可设置锁存器，具有反相器的信号路径和输出逻辑门的所有CMOS逻辑器件组成。单路径耦合到单元单元，可设置锁存器和输出逻辑门，以产生正反馈环路，以提高速度和噪声抗扰度。每个单位逻辑门是用于模块化低功耗，高速，零直流电流，高抗噪声可编程逻辑器件（PLD）的基本构建块，其包括排列成行和列的阵列，用于寻址，或门阵列，以及多个输出逻辑电路。

9. 发明授权

US06411549B1 Reference cell for high speed sensing in non-volatile memories 失效
标题翻译：用于非易失性存储器中高速感测的参考单元
公开(公告)号：US06411549B1
公开(公告)日：2002-06-25
申请号：US09602108
申请日：2000-06-21
申请人： Saroj Pathak , James E. Payne , Jagdish Pathak
发明人： Saroj Pathak , James E. Payne , Jagdish Pathak
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C7/067 , G11C7/14
摘要： A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.
摘要翻译：用于高速感测电路的参考单元包括第一子电路和第二子电路。第一子电路具有类似于主存储器阵列的奇数行内的存储单元的结构。第二子电路具有类似于主存储器阵列的偶数行内的存储单元的结构。如果主存储器阵列内的目标单元位于奇数行内，则选择第一子电路，并且如果目标单元位于偶数行中，则选择第二子电路。第一和第二子电路都包括其控制门分成两部分的参考晶体管。第一部分是聚1层，并且通过隧道氧化物与沟道区分离。第二部分是在第一部分上的金属或聚二层，并且通过栅极氧化物与第一部分分离。通孔用于将第一部分连接到第二部分。

10. 发明授权

US5440508A Zero power high speed programmable circuit device architecture 失效
标题翻译：零功率高速可编程电路器件架构
公开(公告)号：US5440508A
公开(公告)日：1995-08-08
申请号：US194930
申请日：1994-02-09
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： G11C17/00 , G11C14/00 , G11C16/04
CPC分类号： G11C14/00
摘要： A non-volatile, low, and zero power, high speed self-sensing programmable device and architecture including a non-volatile self-sensing cell. The non-volatile self-sensing cell is connected out of the speed path of the programmable device, permitting rapid, non-volatile programming and reading operations to be conducted. According to one version, two self-sensing cells are provided with a means for selecting one of the cells for programming or read operation. Each non-volatile self-sensing cell includes a latch having cross-coupled, pull-up transistors and non-volatile pull-down cells. The cross-coupled pull-up transistors are field effect transistors having gates which are connected to the opposite sources of the cross-coupled pull-up transistors.
摘要翻译：非易失性，低功耗和零功率的高速自感可编程器件和架构，包括非易失性自感应单元。非易失性自感应单元被连接在可编程设备的速度路径之外，允许进行快速，非易失性的编程和读取操作。根据一个版本，两个自感应单元被提供有用于选择一个单元以进行编程或读取操作的装置。每个非易失性自感应单元包括具有交叉耦合的上拉晶体管和非易失性下拉单元的锁存器。交叉耦合上拉晶体管是具有连接到交叉耦合上拉晶体管的相反源极的栅极的场效应晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式