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1. 发明授权

US5936444A Zero power power-on reset circuit 失效
标题翻译：零电源上电复位电路
公开(公告)号：US5936444A
公开(公告)日：1999-08-10
申请号：US977779
申请日：1997-11-25
申请人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Jagdish Pathak , Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.
摘要翻译：上电复位电路包括用于在加电期间建立电荷的第一充电阶段。感测第一充电阶段的上升电压并用于控制用于对第二充电阶段充电的装置。当第二充电阶段达到第一电压电平时，电路跳闸以将第一至第二电荷的电位拉到地。第一充电阶段的接地被反馈到充电装置，其关闭其功率燃烧部件并在第二充电阶段保持第一电压电平。

2. 发明授权

US5963496A Sense amplifier with zero power idle mode 失效
标题翻译：具有零功率空闲模式的感应放大器
公开(公告)号：US5963496A
公开(公告)日：1999-10-05
申请号：US64811
申请日：1998-04-22
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/06 , G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C7/1036
摘要： A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
摘要翻译：用于串行配置存储器的读出放大器包括响应于控制脉冲以控制器方式启用和禁用的多个级。在外部提供的时钟信号的每第N个周期产生控制脉冲，该时钟用于计时表示存储器件的内容的比特流。在优选实施例中，N个这样的感测放大器用于并行地读出构成访问的存储器位置的N个存储器单元（位）。因此，感测放大器仅在足以读出存储器单元的一段时间内是有效的。

3. 发明授权

US5946267A Zero power high speed configuration memory 失效
标题翻译：零功率高速配置存储器
公开(公告)号：US5946267A
公开(公告)日：1999-08-31
申请号：US978286
申请日：1997-11-25
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
IPC分类号： G11C16/02 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
摘要翻译：串行配置存储器件包括以流水线方式执行读出数据和输出比特流的架构。结果，该装置能够仅基于外部提供的时钟的频率输出比特流，并且不受感测放大器电路的较慢的操作速度的限制。提供了一种缓存方案，其允许在复位周期期间预加载第一字节，使得一旦复位周期完成，设备就可以立即开始输出比特流。在本发明的优选实施例中，比特流由从存储器位置零开始的串行访问的存储器位置组成。在一个变型中，比特流可以从除存储器位置零之外的存储器位置开始。

4. 发明授权

US6140993A Circuit for transferring high voltage video signal without signal loss 失效
标题翻译：用于传输高电压视频信号的电路，无信号丢失
公开(公告)号：US6140993A
公开(公告)日：2000-10-31
申请号：US97866
申请日：1998-06-16
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2300/0876 , G09G2310/0289 , G09G3/2011 , G09G3/2074
摘要： A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
摘要翻译：用于传送高压模拟视频信号同时能够使用常规低电压逻辑电平的电路包括由高电压电源供电的第一晶体管，以在高电压电平下偏置传输晶体管。传输晶体管接收高电压视频信号，并且由于高电压偏压能够通过视频信号而不会由于馈通效应而导致信号衰减，从而保持视频信号的保真度。第二晶体管提供接地电位，其操作以关闭传输晶体管，从而禁止视频信号通过其传输。可操作地耦合到第一晶体管的第三晶体管操作以在第二晶体管工作时关断第一晶体管。

5. 发明授权

US6115305A Method and apparatus for testing a video display chip 有权
标题翻译：用于测试视频显示芯片的方法和装置
公开(公告)号：US6115305A
公开(公告)日：2000-09-05
申请号：US333805
申请日：1999-06-15
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G01R31/02 , G01R31/3185 , G09G3/20 , G11C29/02 , G11C29/10 , G11C29/34 , G11C7/00
CPC分类号： G11C29/02 , G01R31/31855
摘要： A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
摘要翻译：视频芯片包括用于检测开路和短路的测试电路。该电路包括串联连接的晶体管链和测试寄存器。列线和行线都有一个电路。位模式被驱动到列或行线上并被接收在相应的测试电路中。该模式被读出并与输入模式进行比较以检测故障线路。

6. 发明申请

US20050140428A1 LOW VOLTAGE CMOS BANDGAP REFERENCE 有权
标题翻译：低电压CMOS贴装参考
公开(公告)号：US20050140428A1
公开(公告)日：2005-06-30
申请号：US10748540
申请日：2003-12-29
申请人： Hieu Tran , Tam Tran , Vishal Sarin , Anh Ly , Nianglamching Hangzo , Sang Nguyen
发明人： Hieu Tran , Tam Tran , Vishal Sarin , Anh Ly , Nianglamching Hangzo , Sang Nguyen
IPC分类号： G05F3/26 , G05F1/10 , G05F3/20 , G05F3/30 , G11C16/30 , H03F3/34
CPC分类号： G05F3/30
摘要： A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.
摘要翻译：带隙参考发生器包括在第一支路中串联连接的pnp双极结型晶体管中的PMOS晶体管和NMOS晶体管。带隙参考发生器包括第二支路，其包括PMOS晶体管，NMOS晶体管，电阻器和pnp双极结型晶体管。偏置电路为由PMOS晶体管的栅极形成的反射镜提供偏置，以降低带隙基准发生器的工作电压。第二偏置电路可以向由NMOS晶体管形成的反射镜提供偏置。提供基于时间的和基于DC偏压的启动电路和方法。

7. 发明授权

US06490212B1 Bitline precharge matching 有权
标题翻译：位线预充电匹配
公开(公告)号：US06490212B1
公开(公告)日：2002-12-03
申请号：US09904160
申请日：2001-07-11
申请人： Hung Q. Nguyen , Nianglamching Hangzo , Sang Thanh Nguyen
发明人： Hung Q. Nguyen , Nianglamching Hangzo , Sang Thanh Nguyen
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C7/062 , G11C7/12 , G11C7/14
摘要： A memory device includes a sense circuit comprising a sense amplifier, a reference sense circuit and a comparator. The sense amplifier detects a signal on a bit line associated with a column of memory cells in a memory array. The reference sense circuit detects a signal on a reference bit line associated with a column of reference cells in the memory array. The comparator compares the outputs of the sense amplifier and the reference sense circuit and provides a signal indicative of the contents of the read memory cell. In response to a transition of an address, the bit line and the reference bit line are precharged prior to reading of the memory cell. The reference sense circuit includes a selectable load that is disabled during the initial time after the address transition so that the bit line and the reference bit line rises substantially identically and then enabled to allow the reference bit line to settle to a steady state.
摘要翻译：存储器件包括读出电路，其包括读出放大器，参考检测电路和比较器。读出放大器检测与存储器阵列中的一列存储器单元相关联的位线上的信号。参考检测电路检测与存储器阵列中的参考单元列相关联的参考位线上的信号。比较器比较读出放大器和参考检测电路的输出，并提供指示读取存储单元的内容的信号。响应于地址的转换，位线和参考位线在读取存储器单元之前被预充电。参考检测电路包括在地址转换之后的初始时间期间禁用的可选负载，使得位线和参考位线基本上相同地上升，然后使能使得参考位线稳定到稳定状态。

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