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1. 发明授权

US06300228B1 Multiple precipitation doping process 失效
标题翻译：多重沉淀掺杂工艺
公开(公告)号：US06300228B1
公开(公告)日：2001-10-09
申请号：US09386089
申请日：1999-08-30
申请人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
发明人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
IPC分类号： H01L2122
CPC分类号： H01L21/268 , H01L21/0455 , H01L21/2255
摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
摘要翻译：用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。然后将衬底（30）退火。退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。退火过程也使非晶区域（32）半导体材料结晶。基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

2. 发明授权

US06338921B1 Mask with linewidth compensation and method of making same 失效
标题翻译：具有线宽补偿的掩模及其制作方法
公开(公告)号：US06338921B1
公开(公告)日：2002-01-15
申请号：US09479150
申请日：2000-01-07
申请人： James A. Bruce , David V. Horak , Randy W. Mann , Jed H. Rankin , Andrew J. Watts
发明人： James A. Bruce , David V. Horak , Randy W. Mann , Jed H. Rankin , Andrew J. Watts
IPC分类号： G03F102
CPC分类号： G03F7/0035 , G03F1/36
摘要： A mask (50′) with linewidth compensation and a method of making same. The mask provides for optimized imaging of isolated patterns (64) and nested patterns (70) present on the same mask. The compensated mask is formed from an uncompensated mask (50) and comprises an upper surface (56) upon which the isolated and nested patterns are formed. The isolated pattern comprises a first segment (76) having first sidewalls (76S). The nested pattern comprises second segments (72) proximate each other and having second sidewalls (72S). A partial conformal layer (86) covers the first segment and has feet (90) outwardly extending a distance d from the first sidewalls along the upper surface. The feet are preferably of a thickness that partially transmits exposure light.
摘要翻译：具有线宽补偿的掩模（50'）及其制造方法。掩模提供对同一掩模上存在的孤立图案（64）和嵌套图案（70）的优化成像。补偿掩模由未补偿的掩模（50）形成，并且包括形成隔离和嵌套图案的上表面（56）。隔离图案包括具有第一侧壁（76S）的第一段（76）。嵌套图案包括彼此靠近并具有第二侧壁（72S）的第二段（72）。部分保形层（86）覆盖第一段并且具有沿着上表面向外延伸距离第一侧壁的距离d的脚（90）。脚部优选地具有部分地透射曝光光的厚度。

3. 发明授权

US06395624B1 Method for forming implants in semiconductor fabrication 失效
标题翻译：在半导体制造中形成植入物的方法
公开(公告)号：US06395624B1
公开(公告)日：2002-05-28
申请号：US09253952
申请日：1999-02-22
申请人： James A. Bruce , Randy W. Mann
发明人： James A. Bruce , Randy W. Mann
IPC分类号： H01L21336
CPC分类号： H01L21/223 , H01L21/268 , Y10S438/952
摘要： The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack. The PGILD process can then be used to form source/drain doped regions on the transistors. The reflective coating reduces the amount of heat absorbed by the gate stack, and thus provides an improved method for fabricating transistors.
摘要翻译：本发明提供了一种克服现有技术方法的缺点的用投影气体浸渍激光掺杂（PGILD）工艺形成植入物的新方法。特别地，优选的方法在施加PGILD激光器之前对反射涂层施加特征。反射涂层降低了由特征吸收的热量，提高了制造工艺的可靠性。优选的方法特别适用于场效应晶体管（FET）的制造。在这种应用中，形成栅极叠层，并且反射涂层在栅极叠层上方。然后将抗反射涂层（ARC）涂覆在反射涂层上。抗反射涂层降低了用于对栅极堆叠进行图案化的光刻工艺的变化。在栅极堆叠被图案化之后，去除抗反射涂层，使反射涂层留在栅极叠层上。然后可以使用PGILD工艺在晶体管上形成源极/漏极掺杂区域。反射涂层减少了栅叠层吸收的热量，因此提供了一种制造晶体管的改进方法。

4. 发明授权

US08569116B2 Integrated circuit with a fin-based fuse, and related fabrication method 有权
标题翻译：具有鳍式保险丝的集成电路及相关制造方法
公开(公告)号：US08569116B2
公开(公告)日：2013-10-29
申请号：US13171228
申请日：2011-06-28
申请人： Randy W. Mann , Kingsuk Maitra , Anurag Mittal
发明人： Randy W. Mann , Kingsuk Maitra , Anurag Mittal
IPC分类号： H01L21/82 , H01L21/479 , H01L21/44
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.
摘要翻译：提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。在该方法中，由半导体材料层产生翅片并具有第一端和第二端。该方法提供了在翅片上从其第一端到其第二端形成导电路径。导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

5. 发明授权

US07696034B2 Methods of base formation in a BiCOMS process 失效
标题翻译： BiCOMS工艺中碱形成的方法
公开(公告)号：US07696034B2
公开(公告)日：2010-04-13
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

6. 发明授权

US06967351B2 Finfet SRAM cell using low mobility plane for cell stability and method for forming 有权
标题翻译： Finfet SRAM单元使用低迁移率平面进行电池稳定性和形成方法
公开(公告)号：US06967351B2
公开(公告)日：2005-11-22
申请号：US10011351
申请日：2001-12-04
申请人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

7. 发明授权

US06881672B2 Selective silicide blocking 失效
标题翻译：选择性硅化物封闭
公开(公告)号：US06881672B2
公开(公告)日：2005-04-19
申请号：US10723700
申请日：2003-11-26
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

8. 发明授权

US06815751B2 Structure for scalable, low-cost polysilicon DRAM in a planar capacitor 失效
标题翻译：在平面电容器中可扩展的低成本多晶硅DRAM的结构
公开(公告)号：US06815751B2
公开(公告)日：2004-11-09
申请号：US10064301
申请日：2002-07-01
申请人： Jeffrey S. Brown , Randy W. Mann
发明人： Jeffrey S. Brown , Randy W. Mann
IPC分类号： H01L218234
CPC分类号： H01L27/10861 , H01L27/0207 , H01L27/1203
摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

9. 发明授权

US06778449B2 Method and design for measuring SRAM array leakage macro (ALM) 失效
标题翻译： SRAM阵列泄漏宏（ALM）测量方法与设计
公开(公告)号：US06778449B2
公开(公告)日：2004-08-17
申请号：US10064302
申请日：2002-07-01
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
摘要翻译：用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。导线将电池连接在一起，就像它们是单个电池一样。导线可以包括通用字线; 一个普通的位线公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

10. 发明授权

US06335272B1 Buried butted contact and method for fabricating 失效
标题翻译：埋地接头和制造方法
公开(公告)号：US06335272B1
公开(公告)日：2002-01-01
申请号：US09637935
申请日：2000-08-14
申请人： Archibald Allen , Jerome B. Lasky , Randy W. Mann , Jed H. Rankin , Francis R. White
发明人： Archibald Allen , Jerome B. Lasky , Randy W. Mann , Jed H. Rankin , Francis R. White
IPC分类号： H01L214763
CPC分类号： H01L21/28512 , H01L21/28518 , H01L21/28568
摘要： A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.
摘要翻译：提供了一种用于其制造的埋地对接接触和方法，其包括具有第一导电类型的掺杂剂并且具有浅沟槽隔离的衬底。第二导电类型的掺杂剂位于所述衬底中的开口的底部。在衬底中的掺杂剂和位于开口的侧壁上的低扩散性掺杂剂之间提供欧姆接触。接触是金属硅化物，金属和/或金属合金。

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