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1. 发明授权

US06700163B2 Selective silicide blocking 有权
标题翻译：选择性硅化物封闭
公开(公告)号：US06700163B2
公开(公告)日：2004-03-02
申请号：US09683278
申请日：2001-12-07
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L2976
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

2. 发明授权

US06825530B1 Zero Threshold Voltage pFET and method of making same 失效
标题翻译：零阈值电压pFET及其制作方法
公开(公告)号：US06825530B1
公开(公告)日：2004-11-30
申请号：US10250190
申请日：2003-06-11
申请人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H Oppold
发明人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H Oppold
IPC分类号： H01L2976
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译：零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与彼此隔开p型衬底材料的口袋。在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

3. 发明授权

US06881672B2 Selective silicide blocking 失效
标题翻译：选择性硅化物封闭
公开(公告)号：US06881672B2
公开(公告)日：2005-04-19
申请号：US10723700
申请日：2003-11-26
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

4. 发明授权

US06815751B2 Structure for scalable, low-cost polysilicon DRAM in a planar capacitor 失效
标题翻译：在平面电容器中可扩展的低成本多晶硅DRAM的结构
公开(公告)号：US06815751B2
公开(公告)日：2004-11-09
申请号：US10064301
申请日：2002-07-01
申请人： Jeffrey S. Brown , Randy W. Mann
发明人： Jeffrey S. Brown , Randy W. Mann
IPC分类号： H01L218234
CPC分类号： H01L27/10861 , H01L27/0207 , H01L27/1203
摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

5. 发明授权

US06778449B2 Method and design for measuring SRAM array leakage macro (ALM) 失效
标题翻译： SRAM阵列泄漏宏（ALM）测量方法与设计
公开(公告)号：US06778449B2
公开(公告)日：2004-08-17
申请号：US10064302
申请日：2002-07-01
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
摘要翻译：用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。导线将电池连接在一起，就像它们是单个电池一样。导线可以包括通用字线; 一个普通的位线公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

6. 发明授权

US07087486B2 Method for scalable, low-cost polysilicon capacitor in a planar DRAM 失效
标题翻译：在平面DRAM中可扩展的低成本多晶硅电容器的方法
公开(公告)号：US07087486B2
公开(公告)日：2006-08-08
申请号：US10963228
申请日：2004-10-12
申请人： Jeffrey S. Brown , Randy W. Mann
发明人： Jeffrey S. Brown , Randy W. Mann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L27/0207 , H01L27/1203
摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.
摘要翻译：提供了增加电容而不损及电池区的电容器结构及其制造方法。第一电容器结构包括存在于半导体衬底中的孔中的绝缘材料，其中每个电容器孔的底壁上的绝缘材料与每个孔的侧壁相比较厚。在另一个电容器结构中，提供深电容器孔，其具有存在于每个孔下方的隔离植入区。

7. 发明授权

US07005334B2 Zero threshold voltage pFET and method of making same 失效
标题翻译：零阈值电压pFET及其制作方法
公开(公告)号：US07005334B2
公开(公告)日：2006-02-28
申请号：US10845835
申请日：2004-05-14
申请人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H. Oppold
发明人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H. Oppold
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译：零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与彼此隔开p型衬底材料的口袋。在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

8. 发明申请

US20120119788A1 On-chip Power Supply Monitoring Using a Network of Modulators 有权
标题翻译：使用调制器网络进行片上电源监控
公开(公告)号：US20120119788A1
公开(公告)日：2012-05-17
申请号：US12947890
申请日：2010-11-17
申请人： Mark Franklin Turner , Jeffrey S. Brown , Jonathan W. Byrn
发明人： Mark Franklin Turner , Jeffrey S. Brown , Jonathan W. Byrn
IPC分类号： G01R19/00 , H03K5/22
CPC分类号： G01R19/16552
摘要： An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.
摘要翻译：用于至少监视IC中的电源电压的装置包括分布在整个集成电路中的多个监视电路。每个监视器电路都可操作以接收电源电压或代表其的信号，并产生指示电源电压和参考电压之间的比较的输出信号。该装置还包括耦合到多个监视器电路的控制电路。控制电路可操作以从多个监视器电路接收相应的输出信号，并产生该装置的输出，该输出是来自多个监视器电路的相应输出信号中传送的信息的函数。

9. 发明申请

US20100007371A1 TESTABLE TRISTATE BUS KEEPER 有权
标题翻译：可测试的三脚座保险丝
公开(公告)号：US20100007371A1
公开(公告)日：2010-01-14
申请号：US12169216
申请日：2008-07-08
申请人： Jeffrey S. Brown , Mark F. Turner , Marek J. Marasch
发明人： Jeffrey S. Brown , Mark F. Turner , Marek J. Marasch
IPC分类号： H03K19/00
CPC分类号： G01R31/318544
摘要： A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.
摘要翻译：一种通过向三态施加给定值来测试三态元件的方法，对连接在三态输出端的保持器元件施加相反的值，在三态的下游位置处捕获第一值，评估第三值的第二值使用第一值的三态输出，将第二值与相反值进行比较，并且当第二值不等于相反值时，产生三态的故障代码。然后，将相反的值应用于三态，将给定值应用于保持器元件，捕获第一值，使用第一值来评估第二值，将第二值与给定值进行比较，并产生三态的故障代码当第二个值不等于给定值时。当没有产生故障代码时，产生三态的传递代码。

10. 发明授权

US07567478B2 Leakage optimized memory 失效
标题翻译：泄漏优化内存
公开(公告)号：US07567478B2
公开(公告)日：2009-07-28
申请号：US11868576
申请日：2007-10-08
申请人： Jeffrey S. Brown
发明人： Jeffrey S. Brown
IPC分类号： G11C5/14 , G11C8/14
CPC分类号： G11C5/02 , G06F2217/78 , G11C17/10
摘要： A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing only padding data, (B) adjusting the design such that a second power consumption in each of the second rows is lower than a first power consumption in each of the first rows and (C) generating a file defining the design as adjusted.
摘要翻译：公开了一种存储器中功率优化的方法。该方法通常包括以下步骤：（A）将存储器设计中的多个比特单元划分为（i）存储编程数据的多个第一行和（ii）仅存储填充数据的至少一个第二行（B ）调整所述设计，使得每个所述第二行中的第二功率消耗低于所述第一行中的每一个中的第一功率消耗，以及（C）生成定义被调整的设计的文件。

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