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1. 发明授权

US06707822B1 Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method 失效
标题翻译：多会话非对称数字用户线缓冲和调度设备及方法
公开(公告)号：US06707822B1
公开(公告)日：2004-03-16
申请号：US09479611
申请日：2000-01-07
申请人： Jalil Fadavi-Ardekani , Walter G. Soto , Weizhuang Xin
发明人： Jalil Fadavi-Ardekani , Walter G. Soto , Weizhuang Xin
IPC分类号： H04B138
CPC分类号： H04L25/05 , H04L1/004 , H04L5/14
摘要： A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI. IDIM holds DMT frames of data and may also be utilized in a ping-pang fashion. Memory is shared by multiple ADSL sessions and by the transmit and receive processes within an individual session.
摘要翻译：提供了一种用于非对称通信系统的收发器，其实现了利用虚拟时钟信号来同步多个ADSL会话的异步帧数据的处理的缓冲和调度方案。在每个虚拟时钟周期中，收发器首先对每个活动ADSL线路顺序执行发送处理，然后对每个活动的ADSL线路顺序执行接收处理。异步传输模式（ATM）Acceleratol提供到多个ATM信道的网络接口，并将帧数据传送到帧缓冲区（FB）。 FB可以以乒乓方式用于ATM加速器与执行其同名功能的成帧器/编码器/交织器（FCI）之间的数据通信。 FCI还通过Interleave / De-Interleave Memory（IDIM）将数字信号处理（DSP）核心接口。 DSP内核生成虚拟时钟信号，该时钟信号调度ATM加速器和FCI的操作。 IDIM拥有DMT数据帧，也可以以乒乓方式使用。内存由多个ADSL会话以及单个会话中的发送和接收进程共享。

2. 发明授权

US06842844B1 Parameter memory for hardware accelerator 失效
标题翻译：硬件加速器的参数存储器
公开(公告)号：US06842844B1
公开(公告)日：2005-01-11
申请号：US09512511
申请日：2000-02-24
申请人： Jalil Fadavi-Ardekani , Walter G. Soto , Wayne Xin
发明人： Jalil Fadavi-Ardekani , Walter G. Soto , Wayne Xin
IPC分类号： G06F13/40 , G06F15/17 , G06F15/177 , H04M11/06
CPC分类号： H04M11/062
摘要： The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.
摘要翻译：本发明提供了具有参数RAM存储器的DSP的硬件加速器，用于存储加速器的各种操作条件所需的参数。硬件加速器可以轻松而无需修改，可以满足设计更改，例如需要支持额外的ADSL线路。

3. 发明授权

US06230215B1 On-demand transfer engine 有权
标题翻译：按需传输引擎
公开(公告)号：US06230215B1
公开(公告)日：2001-05-08
申请号：US09188904
申请日：1998-11-10
申请人： Jalil Fadavi-Ardekani , Srinivasa Gutta , Walter G. Soto , Avinash Velingker , Daniel K. Greenwood
发明人： Jalil Fadavi-Ardekani , Srinivasa Gutta , Walter G. Soto , Avinash Velingker , Daniel K. Greenwood
IPC分类号： G06F300
CPC分类号： G06F1/3237 , G06F1/3203 , G06F11/349 , G06F12/0646 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278 , Y02D10/128 , Y02D10/34
摘要： An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.
摘要翻译：按需传输（ODT）引擎位于使用突发模式总线（例如PCI总线）通信的主机/外围设备系统的每个外围设备中。每个外设通过设置例如要传送的数据块的起始地址和块大小来传送块。重要的是，数据传输流的起始位置保持在公共存储器区域中，例如在主机中，而数据传输块的长度保持在ODT引擎中。通过保持ODT引擎中数据块的长度，外设可以随时更改连续数据流中块的长度，而无需与主机或公共数据传输设备（如DMA）通信。在所公开的实施例中，多达128个数据流可以被同时传送。

4. 发明授权

US06965974B1 Dynamic partitioning of memory banks among multiple agents 失效
标题翻译：内存库在多个代理之间进行动态分区
公开(公告)号：US06965974B1
公开(公告)日：2005-11-15
申请号：US09120126
申请日：1998-07-22
申请人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Srinivasa Gutta , Bahram Ghaffarzadeh Kermani , Richard Joseph Niescier , Geoffrey Lawrence Smith , Walter G. Soto , Daniel K. Greenwood
发明人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Srinivasa Gutta , Bahram Ghaffarzadeh Kermani , Richard Joseph Niescier , Geoffrey Lawrence Smith , Walter G. Soto , Daniel K. Greenwood
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/0607
摘要： A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.
摘要翻译：提供多个代理（例如处理器）中的每一个以访问共享同步或异步存储器的多代理系统。在同步存储器的情况下，从多个代理中选择的来自超级代理的时钟信号向访问同一共享存储器的其他代理提供存储器访问时钟信号。其他代理将其各自的地址，数据和控制总线同步到超级代理的总线，并将相同时钟信号的表示输出到共享存储器。在本发明的另一方面，共享存储器被划分为在多组代理之间使用，每个代理组包括一个或多个代理。任何一个代理可以更新配置寄存器，以便根据需要灵活地重新配置代理可用的共享内存量。

5. 发明授权

US06499087B1 Synchronous memory sharing based on cycle stealing 失效
标题翻译：基于循环窃取的同步存储器共享
公开(公告)号：US06499087B1
公开(公告)日：2002-12-24
申请号：US09093859
申请日：1998-06-09
申请人： Jalil Fadavi-Ardekani , Bahram Kermani , Walter G. Soto , Richard J. Niescier , Fan You
发明人： Jalil Fadavi-Ardekani , Bahram Kermani , Walter G. Soto , Richard J. Niescier , Fan You
IPC分类号： G06F1318
CPC分类号： G06F13/4018 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278
摘要： A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated when the super agent is not, accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even, before the super agent terminates ownership of the shared synchronous memory.
摘要翻译：提供多个代理（即，处理器）中的每一个的多代理系统对共享同步存储器的访问。超级代理优选地是来自最频繁访问共享同步存储器的多个代理中的代理。超级代理可以直接访问共享同步存储器，而无需协商和/或仲裁，而非超级代理在仲裁器和交换机的控制下访问共享同步存储器。当超级代理没有访问共享同步存储器时，会产生打开的窗口。即使在超级代理终止共享同步存储器的所有权之前，也可以允许非超级代理人临时访问共享同步存储器。

6. 发明授权

US06401176B1 Multiple agent use of a multi-ported shared memory 失效
标题翻译：多代理使用多端口共享内存
公开(公告)号：US06401176B1
公开(公告)日：2002-06-04
申请号：US09098503
申请日：1998-06-17
申请人： Jalil Fadavi-Ardekani , Walter G. Soto
发明人： Jalil Fadavi-Ardekani , Walter G. Soto
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G06F13/1663
摘要： A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter and switch. Open windows are generated when the super agent is not accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even before the super agent terminates ownership of the shared synchronous memory. In another aspect of the present invention, subsequent memory access request signals from an agent to the shared synchronous memory are suppressed for a minimum refractory period until a previously received acknowledge signal is cleared to prevent erroneous detection of memory access granted.
摘要翻译：提供多个代理（即，处理器）中的每一个的多代理系统对共享同步存储器的访问。超级代理优选地是来自最频繁访问共享同步存储器的多个代理中的代理。超级代理可以直接访问共享同步存储器，而无需协商和/或仲裁，而非超级代理在仲裁器和交换机的控制下访问共享同步存储器。当超级代理未访问共享同步存储器时，会生成打开的窗口。即使在超级代理终止共享同步存储器的所有权之前，非超级代理可以被允许临时访问共享同步存储器。在本发明的另一方面，从代理到共享同步存储器的后续存储器访问请求信号被抑制到最小不可逆期，直到先前接收到的确认信号被清除以防止被许可的存储器访问的错误检测。

7. 发明授权

US6067317A Computer bus resource port 失效
标题翻译：计算机总线资源端口
公开(公告)号：US6067317A
公开(公告)日：2000-05-23
申请号：US649095
申请日：1996-05-17
申请人： Jalil Fadavi-Ardekani , Kenneth D. Fitch , Walter G. Soto
发明人： Jalil Fadavi-Ardekani , Kenneth D. Fitch , Walter G. Soto
IPC分类号： H04B1/38
CPC分类号： H04M11/066
摘要： A resource port that provides a host processor the facility to request, share and access the resources of data communication equipment (DCE), including the memory and I/O registers of the DCE controller. In one embodiment the resource port has a controller request line to provide the host with a facility to request access to the controller resources, and an interface circuit to provide the facility to index all the resources of the DCE. The interface circuit compensates for any disparity between the widths of the controller address bus and the host processor address bus, and between the widths of the host processor data bus and the controller data bus.
摘要翻译：为主处理器提供请求，共享和访问数据通信设备（DCE）的资源（包括DCE控制器的存储器和I / O寄存器）的资源的资源端口。在一个实施例中，资源端口具有控制器请求线，以向主机提供请求对控制器资源的访问的设施，以及接口电路，用于为DCE的所有资源提供索引。接口电路补偿控制器地址总线和主处理器地址总线的宽度之间以及主机处理器数据总线和控制器数据总线的宽度之间的任何差异。

8. 发明授权

US06279048B1 System wake-up based on joystick movement 失效
标题翻译：系统唤醒基于操纵杆移动
公开(公告)号：US06279048B1
公开(公告)日：2001-08-21
申请号：US09110673
申请日：1998-07-07
申请人： Jalil Fadavi-Ardekani , David Lawson Potts , Walter G. Soto , Avinash Velingker
发明人： Jalil Fadavi-Ardekani , David Lawson Potts , Walter G. Soto , Avinash Velingker
IPC分类号： G06F300
CPC分类号： G06F3/0383 , G06F1/3215 , G06F1/3259 , G06F11/349 , G06F12/0646 , G06F2201/88 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278 , Y02D10/155 , Y02D10/34 , Y02D50/20
摘要： The present invention provides a game port interface having a second processor interface in addition to an otherwise conventional first processor interface such that a second processor may directly poll the game port interface to detect movement of a joystick device while a first, host processor is in a low power mode. Thus, the second processor may identify movement in the joystick and initiate a wake up sequence in the first, host processor via a communication path between the two processor interfaces. The additional processor interface allows the second processor to poll the joystick without interfering with the normal operation of the joystick. The present invention provides the power savings benefits of maintaining a host processor in a low power mode while at the same allowing another processor which may or may not be in a reduced power mode to detect movement of the joystick and initiate a wake up sequence in the host processor in response thereto.
摘要翻译：本发明提供一种游戏端口接口，除了传统的第一处理器接口之外还具有第二处理器接口，使得第二处理器可以直接轮询游戏端口接口来检测操纵杆设备的移动，同时第一主机处理器处于低功耗模式。因此，第二处理器可以识别操纵杆中的移动，并且经由两个处理器接口之间的通信路径在第一主处理器中发起唤醒序列。附加处理器接口允许第二处理器轮询操纵杆，而不会妨碍操纵杆的正常操作。本发明提供了将主机处理器维持在低功率模式中的功率节省优点，同时允许可能或可能不处于降低功率模式的另一处理器来检测操纵杆的移动并启动操纵杆中的唤醒序列主机处理器。

9. 发明授权

US5754590A Modem architecture for integrated controller and data pump applications 失效
标题翻译：集成控制器和数据泵应用的调制解调器架构
公开(公告)号：US5754590A
公开(公告)日：1998-05-19
申请号：US649367
申请日：1996-05-17
申请人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Walter G. Soto
发明人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Walter G. Soto
IPC分类号： H04L5/16
CPC分类号： H04M11/066
摘要： A new modem architecture that substantially minimizes the cost of adding features to the modem, and substantially minimizes the time overhead associated with the slave-like interface between the modem controller and the modem signal processor. The architecture enables the signal processor to directly access the controller's memory resources so that the signal processor can make most efficient use of its own internal expensive high-speed memory.
摘要翻译：一种新的调制解调器架构，其基本上最小化向调制解调器添加特征的成本，并且基本上最小化与调制解调器控制器和调制解调器信号处理器之间的从属接口相关联的时间开销。该架构使信号处理器能够直接访问控制器的存储器资源，使信号处理器能够最有效地利用自己内部昂贵的高速存储器。

10. 发明申请

US20140314412A1 SYSTEM AND METHOD FOR A SUBSCRIBER-POWERED NETWORK ELEMENT 审中-公开
标题翻译：用户订购网络元件的系统和方法
公开(公告)号：US20140314412A1
公开(公告)日：2014-10-23
申请号：US14025804
申请日：2013-09-12
申请人： Alexander I. Soto , Walter G. Soto
发明人： Alexander I. Soto , Walter G. Soto
IPC分类号： H04B10/80 , H04B10/27
CPC分类号： H04B10/808 , H04B10/07955 , H04B10/272 , H04B10/806 , H04L12/10 , H04L12/2898 , H04M19/08
摘要： A system for powering a network element of a fiber optic wide area network is disclosed. When communication data is transferred between a central office (CO) and a subscriber terminal using a network element to convert optical to electrical (O-E) and electrical to optical (E-O) signals between a fiber from the central office and twisted wire pair, coaxial cable or Ethernet cable transmission lines from the subscriber terminal, techniques related to local powering of a network element or drop site by the subscriber terminal or subscriber premise remote powering device are provided. Certain advantages and/or benefits are achieved using the present invention, such as freedom from any requirement for additional meter installations or meter connection charges and does not require a separate power network.
摘要翻译：公开了一种用于为光纤广域网的网络元件供电的系统。当使用网络元件在中心局（CO）和用户终端之间传送通信数据以在中心局的光纤和双绞线对之间转换光学到电（OE）和电 - 光（EO）信号时，同轴电缆或来自用户终端的以太网电缆传输线，提供与用户终端或用户驻地远程供电设备对网元或丢弃站点的本地供电有关的技术。使用本发明实现了某些优点和/或益处，例如不需要额外的仪表安装或仪表连接费用，并且不需要单独的电力网络。

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