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1. 发明授权

US5541943A Watchdog timer lock-up prevention circuit 失效
标题翻译：看门狗定时器锁定防止电路
公开(公告)号：US5541943A
公开(公告)日：1996-07-30
申请号：US349346
申请日：1994-12-02
申请人： Richard J. Niescier , Mohit K. Prasad
发明人： Richard J. Niescier , Mohit K. Prasad
IPC分类号： G06F11/30 , G05B19/048 , G05B19/05 , G06F9/48 , G06F11/00
CPC分类号： G06F11/0757
摘要： A lock-up prevention circuit and method are used with a watchdog timer circuit. The lock-up prevention circuit includes a logic circuit for receiving a first signal for generating an enabling signal, and responds to a first predetermined bit stored in a control register for controlling a loading of an enabling signal to the control register. The watchdog timer circuit responds to the loading of the enabling signal to be enabled to respond to a second predetermined bit of the control register for controlling initiation of a timing cycle of the watchdog timer circuit. In response to a clock signal and a second predetermined bit of the control register, the logic circuit clocks the control register to load the enabling signal. The method prevents lock-up in a watchdog timer circuit, and includes the steps of receiving a first signal; generating an enabling signal using the first signal; controlling a control register to load the enabling signal thereto; enabling the watchdog timer circuit to respond to a predetermined bit of the control register; and controlling initiation of a timing cycle of the watchdog timer circuit. The step of receiving the first signal includes the step of receiving either a watchdog mode select signal or a timer enable signal; and the step of generating the enabling signal includes the step of generating the enabling signal from the received at least one of the watchdog mode select signal and the timer enable signal. Input lines IDB12 and IDB15 are ORed to set a TIMER.
摘要翻译：看门狗定时器电路使用锁定防止电路和方法。锁定防止电路包括用于接收用于产生使能信号的第一信号的逻辑电路，并且对存储在控制寄存器中的第一预定位进行响应，以控制向控制寄存器加载使能信号。看门狗定时器电路响应使能信号的加载以使得能够响应控制寄存器的第二预定位，以控制看门狗定时器电路的定时周期的启动。响应于控制寄存器的时钟信号和第二预定位，逻辑电路对控制寄存器进行时钟以加载使能信号。该方法防止看门狗定时器电路中的锁定，并且包括接收第一信号的步骤; 使用所述第一信号产生使能信号; 控制控制寄存器以将启用信号加载到其上; 使看门狗定时器电路响应控制寄存器的预定位; 以及控制看门狗定时器电路的定时周期的启动。接收第一信号的步骤包括接收看门狗模式选择信号或定时器使能信号的步骤; 并且产生使能信号的步骤包括从所接收到的看门狗模式选择信号和定时器使能信号中的至少一个产生使能信号的步骤。输入行IDB12和IDB15被置为“定时器”。

2. 发明申请

US20080122474A1 SYSTEMS AND METHODS FOR REDUCING THE EFFECTS OF ELECTROSTATIC DISCHARGE 审中-公开
标题翻译：减少静电放电效果的系统和方法
公开(公告)号：US20080122474A1
公开(公告)日：2008-05-29
申请号：US11563264
申请日：2006-11-27
申请人： Che Choi C. Leung , Richard J. Niescier , Yehuda Smooha
发明人： Che Choi C. Leung , Richard J. Niescier , Yehuda Smooha
IPC分类号： G01R31/26 , H02H9/00
CPC分类号： G01R31/002
摘要： Various systems and methods for limiting the effects of electrostatic discharge are disclosed. For example, a system for reducing the effects of electrostatic discharge is disclosed that includes at least two isolated pairs of potential planes. The two isolated pairs of potential planes may include, but are not limited to, a first VDD plane paired with a first VSS plane may be isolated from a second VDD plane that is paired with a second VSS plane. One circuit in the system is powered by a differential between one pair of the potential planes, and another circuit is powered by a differential between the other pair of potential planes. In addition, the system includes a transitional circuit that receives a signal output from the first of the aforementioned circuits, and provides a signal input to the second of the aforementioned circuits. The transitional circuit is powered by a differential between one potential plane from one of the pairs of potential planes, and one potential plane from another of the pairs of potential planes.
摘要翻译：公开了用于限制静电放电效果的各种系统和方法。例如，公开了一种减少静电放电效应的系统，其包括至少两个隔离的电位平面对。两个隔离的电位平面对可以包括但不限于与第一VSS平面配对的第一VDD平面可以与与第二VSS平面配对的第二VDD平面隔离。系统中的一个电路由一对电位平面之间的差分供电，另一个电路由另一对电位平面之间的差分供电。此外，该系统包括接收从上述第一电路输出的信号的过渡电路，并向上述电路的第二个提供信号输入。过渡电路由来自一对电位平面的一个电位平面与来自另一对电位平面的一个电位平面之间的差分供电。

3. 发明授权

US06499087B1 Synchronous memory sharing based on cycle stealing 失效
标题翻译：基于循环窃取的同步存储器共享
公开(公告)号：US06499087B1
公开(公告)日：2002-12-24
申请号：US09093859
申请日：1998-06-09
申请人： Jalil Fadavi-Ardekani , Bahram Kermani , Walter G. Soto , Richard J. Niescier , Fan You
发明人： Jalil Fadavi-Ardekani , Bahram Kermani , Walter G. Soto , Richard J. Niescier , Fan You
IPC分类号： G06F1318
CPC分类号： G06F13/4018 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278
摘要： A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated when the super agent is not, accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even, before the super agent terminates ownership of the shared synchronous memory.
摘要翻译：提供多个代理（即，处理器）中的每一个的多代理系统对共享同步存储器的访问。超级代理优选地是来自最频繁访问共享同步存储器的多个代理中的代理。超级代理可以直接访问共享同步存储器，而无需协商和/或仲裁，而非超级代理在仲裁器和交换机的控制下访问共享同步存储器。当超级代理没有访问共享同步存储器时，会产生打开的窗口。即使在超级代理终止共享同步存储器的所有权之前，也可以允许非超级代理人临时访问共享同步存储器。

4. 发明授权

US06297751B1 Low-voltage joystick port interface 失效
标题翻译：低压操纵杆端口接口
公开(公告)号：US06297751B1
公开(公告)日：2001-10-02
申请号：US09113503
申请日：1998-07-10
申请人： Jalil Fadavi-Ardekani , Raymond S. Livingston , Richard J. Niescier , David L. Potts
发明人： Jalil Fadavi-Ardekani , Raymond S. Livingston , Richard J. Niescier , David L. Potts
IPC分类号： H03L500
CPC分类号： G06F3/038
摘要： The joystick port interface includes an integrated circuit receiving an analog joystick position measurement signal and outputting a digital pulse signal to a processor which signifies a joystick coordinate value. The integrated circuit includes a pulse generator and a bidirectional buffer circuit. The bidirectional buffer circuit receives the analog joystick position measurement signal and selectively discharges an RC network capacitor which provides this analog measurement. This implementation provides a joystick port which uses low-voltage CMOS VLSI structures which can interface a conventional high-voltage joystick with the processor.
摘要翻译：操纵杆端口接口包括接收模拟操纵杆位置测量信号并将数字脉冲信号输出到表示操纵杆坐标值的处理器的集成电路。集成电路包括脉冲发生器和双向缓冲电路。双向缓冲电路接收模拟操纵杆位置测量信号，并选择性地放电提供该模拟测量的RC网络电容器。该实现提供了一个操纵杆端口，它使用低电压CMOS VLSI结构，可以将传统的高压操纵杆与处理器接口。

5. 发明授权

US06266751B1 Continuously sliding window method and apparatus for sharing single-ported memory banks between two agents 有权
标题翻译：连续滑动窗口方法和装置，用于在两个代理之间共享单端口存储器组
公开(公告)号：US06266751B1
公开(公告)日：2001-07-24
申请号：US09141510
申请日：1998-08-27
申请人： Richard J. Niescier
发明人： Richard J. Niescier
IPC分类号： G06F1200
CPC分类号： G06F12/0284 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278
摘要： A shared memory system configurably partitioned to assign a pre-defined number of memory banks to a first processing agent and the remaining memory banks to a second processing agent. The first group of memory banks is assigned into the memory map of the first processing agent in increasing order while the second group of memory banks is assigned into the memory map of the second processing agent in decreasing order. In more general terms, in a shared memory bank system having M memory banks, a first processing agent will own memory banks 1 through N starting at its address 0, and a second processing agent will own memory banks M to N+1, respectively, starting at its address 0.
摘要翻译：共享存储器系统可配置地分区以将预定数量的存储体分配给第一处理代理，并且剩余的存储体分配给第二处理代理。第一组存储体被分配到第一处理代理的存储器映射中，而第二组存储体被分配到第二处理代理的存储器映射中。在更一般的术语中，在具有M个存储体的共享存储体系统中，第一处理代理将从其地址0开始拥有存储体1至N，并且第二处理代理将分别拥有存储体M至N + 1，从地址0开始。

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