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1. 发明授权

US07612435B2 Method of packaging integrated circuits 有权
标题翻译：集成电路封装方法
公开(公告)号：US07612435B2
公开(公告)日：2009-11-03
申请号：US11963388
申请日：2007-12-21
申请人： Jaime A. Bayan , Anindya Poddar
发明人： Jaime A. Bayan , Anindya Poddar
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3185 , H01L23/49537 , H01L2224/16 , H01L2224/16245 , H01L2924/09701 , H01L2924/19041
摘要： A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.
摘要翻译：描述了一种封装具有多个I / O焊盘的集成电路管芯的方法。该方法包括将管芯定位在包括多个第一引线的第一引线框的管芯附着区域内。该方法还包括在第一引线框上定位包括多个第二引线的第二引线框架。该方法还包括将每个第二引线电连接到相关联的I / O焊盘和第一引线。

2. 发明授权

US07923825B2 Integrated circuit package 有权
标题翻译：集成电路封装
公开(公告)号：US07923825B2
公开(公告)日：2011-04-12
申请号：US12553919
申请日：2009-09-03
申请人： Jaime A. Bayan , Anindya Poddar
发明人： Jaime A. Bayan , Anindya Poddar
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3185 , H01L23/49537 , H01L2224/16 , H01L2224/16245 , H01L2924/09701 , H01L2924/19041
摘要： An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.
摘要翻译：描述了一种集成电路封装，其包括集成电路管芯，多个下接触引线和位于管芯和下接触引线上的绝缘基片。绝缘基板包括形成在基板的底表面上的多个导电上路由迹线。衬底底面上的迹线将每个下接触引线与相关的I / O焊盘电耦合。

3. 发明授权

US07705476B2 Integrated circuit package 有权
标题翻译：集成电路封装
公开(公告)号：US07705476B2
公开(公告)日：2010-04-27
申请号：US11936017
申请日：2007-11-06
申请人： Jaime A. Bayan , Anindya Poddar
发明人： Jaime A. Bayan , Anindya Poddar
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/4952 , H01L23/49572 , H01L24/15 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/16145 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.
摘要翻译：描述了集成电路（IC）封装。每个IC封装包括具有沉积在其背面上的暴露的金属层的裸片。焊接点布置成物理和电连接管芯有源表面上的I / O焊盘与相关引线。模制材料封装模具的一部分，引线框架和焊接接头连接，同时使金属层暴露和未被模制材料覆盖。

4. 发明授权

US07491625B2 Gang flipping for IC packaging 有权
标题翻译：帮派翻转用于IC封装
公开(公告)号：US07491625B2
公开(公告)日：2009-02-17
申请号：US11691431
申请日：2007-03-26
申请人： Jaime A. Bayan , Nghia Tu , Anindya Poddar , Ashok Prabhu
发明人： Jaime A. Bayan , Nghia Tu , Anindya Poddar , Ashok Prabhu
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/6836 , H01L24/81 , H01L2221/68327 , H01L2221/68354 , H01L2224/16 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.
摘要翻译：描述了处理包括多个骰子的IC晶片的方法。焊料凸起形成在晶片的有源表面上的接合焊盘上。凸起的晶片的背面粘附到第一安装带。在晶片仍被固定到第一磁带的同时将晶片单片化以提供多个独立的骰子。然后将分割的骰子的活性表面粘附到第二带上，其中第一带仍然粘附到骰子的后表面。然后可以移除第一个磁带。以这种方式，骰子的后表面可以被暴露并且面向上并且骰子的活动表面粘附到第二带上。所描述的方法允许使用未被指定用作倒装芯片连接机的常规的芯片连接机。

5. 发明申请

US20090115035A1 INTEGRATED CIRCUIT PACKAGE 有权
标题翻译：集成电路封装
公开(公告)号：US20090115035A1
公开(公告)日：2009-05-07
申请号：US11936017
申请日：2007-11-06
申请人： Jaime A. BAYAN , Anindya Poddar
发明人： Jaime A. BAYAN , Anindya Poddar
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/4952 , H01L23/49572 , H01L24/15 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/16145 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.
摘要翻译：描述了集成电路（IC）封装。每个IC封装包括具有沉积在其背面上的暴露的金属层的裸片。焊接点布置成物理和电连接管芯有源表面上的I / O焊盘与相关引线。模制材料封装模具的一部分，引线框架和焊接接头连接，同时使金属层暴露和未被模制材料覆盖。

6. 发明申请

US20080241993A1 GANG FLIPPING FOR IC PACKAGING 有权
标题翻译：缉拿包装IC
公开(公告)号：US20080241993A1
公开(公告)日：2008-10-02
申请号：US11691431
申请日：2007-03-26
申请人： Jaime A. Bayan , Nghia Tu , Anindya Poddar , Ashok Prabhu
发明人： Jaime A. Bayan , Nghia Tu , Anindya Poddar , Ashok Prabhu
IPC分类号： H01L21/58
CPC分类号： H01L21/6835 , H01L21/6836 , H01L24/81 , H01L2221/68327 , H01L2221/68354 , H01L2224/16 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.
摘要翻译：描述了处理包括多个骰子的IC晶片的方法。焊料凸起形成在晶片的有源表面上的接合焊盘上。凸起晶片的背面粘附到第一安装带。在晶片仍被固定到第一磁带的同时将晶片单片化以提供多个独立的骰子。然后将分割的骰子的活性表面粘附到第二带上，其中第一带仍然粘附到骰子的后表面。然后可以移除第一个磁带。以这种方式，骰子的后表面可以被暴露并且面向上并且骰子的活动表面粘附到第二带上。所描述的方法允许使用未被指定用作倒装芯片连接机的常规的芯片连接机。

7. 发明申请

US20080241991A1 GANG FLIPPING FOR FLIP-CHIP PACKAGING 审中-公开
标题翻译：襟翼包装的缉拿
公开(公告)号：US20080241991A1
公开(公告)日：2008-10-02
申请号：US11691428
申请日：2007-03-26
申请人： Anindya Poddar , Jaime A. Bayan , Ashok S. Prabhu , Will K. Wong
发明人： Anindya Poddar , Jaime A. Bayan , Ashok S. Prabhu , Will K. Wong
IPC分类号： H01L21/00
CPC分类号： H01L23/49548 , H01L21/561 , H01L24/13 , H01L24/81 , H01L24/97 , H01L2221/68354 , H01L2224/11822 , H01L2224/16245 , H01L2224/81001 , H01L2224/81011 , H01L2224/81801 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/81 , H01L2224/0401
摘要： An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas.
摘要翻译：描述了用于封装集成电路的改进的方法和装置。更具体地，描述了用于将多个集成电路芯片固定到引线框架面板的方法和装置。每个集成电路管芯包括具有多个焊料凸点的有源表面。引线框架面板包括一组设备区域，每个设备区域包括多个引线。该方法包括将多个骰子定位在载体上的指定位置，使得骰子的活动表面朝上。载体包括载体框架，其包括相关的载体装置区域阵列。引线框架面板可以定位在载体上方，使得骰子的有效表面上的焊料凸块相邻并与相关联的器件区域的相关引线接触。

8. 发明申请

US20130127008A1 THERMALLY EFFICIENT INTEGRATED CIRCUIT PACKAGE 有权
标题翻译：高效集成电路封装
公开(公告)号：US20130127008A1
公开(公告)日：2013-05-23
申请号：US13304167
申请日：2011-11-23
申请人： Anindya Poddar , Luu T. Nguyen
发明人： Anindya Poddar , Luu T. Nguyen
IPC分类号： H01L21/60 , H01L23/482
CPC分类号： H01L23/3121 , H01L21/561 , H01L23/3735 , H01L23/4334 , H01L23/49575 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/84 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/291 , H01L2224/2919 , H01L2224/32227 , H01L2224/32245 , H01L2224/371 , H01L2224/4005 , H01L2224/40106 , H01L2224/40108 , H01L2224/40225 , H01L2224/40245 , H01L2224/40479 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/81191 , H01L2224/81815 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92225 , H01L2224/92226 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.
摘要翻译：在本发明的一个方面中，将描述集成电路封装。集成电路封装包括至少两个与基板连接的集成电路。集成电路和基板至少部分地封装在模制材料中。存在部分延伸穿过模制材料并且被布置成在集成电路之间形成热障碍物的凹槽或气隙。

9. 发明授权

US07824963B2 Inkjet printed leadframe 有权
标题翻译：喷墨印刷引线框
公开(公告)号：US07824963B2
公开(公告)日：2010-11-02
申请号：US12626440
申请日：2009-11-25
申请人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
发明人： Randall L. Walberg , Luu T. Nguyen , Anindya Poddar
IPC分类号： H01L21/44 , H01L23/495
CPC分类号： H01L21/4821 , H01L21/6835 , H01L23/49579 , H01L24/97 , H01L2221/68345 , H01L2924/14 , H01L2924/00
摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.
摘要翻译：公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。然后将nanoink固化以除去液体内容物。剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个单独的器件阵列包括多个电互连图案，每个均包括安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关联的电互连图案的模制帽。模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

10. 发明申请

US20090174069A1 I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：集成电路设备中提高焊接点可靠性的I / O PAD结构
公开(公告)号：US20090174069A1
公开(公告)日：2009-07-09
申请号：US11969704
申请日：2008-01-04
申请人： Hau Nguyen , Luu T. Nguyen , Anindya Poddar
发明人： Hau Nguyen , Luu T. Nguyen , Anindya Poddar
IPC分类号： H01L23/488
CPC分类号： H01L24/16 , H01L24/05 , H01L2224/0401 , H01L2224/05082 , H01L2224/05624 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device is described. The device includes an integrated circuit die having an active surface that includes a plurality of input/output (I/O) pads. The device further includes a plurality of crack resistant structures. Each crack resistant structure is formed over an associated I/O pad and includes an associated raised portion. Each I/O pad may be bumped with solder such that a solder bump is formed over the associated crack resistant structure on the I/O pad.
摘要翻译：描述半导体器件。该器件包括具有包括多个输入/输出（I / O）焊盘的有源表面的集成电路管芯。该装置还包括多个抗裂结构。每个抗裂结构都形成在相关的I / O焊盘上，并且包括相关联的凸起部分。每个I / O焊盘可能被焊接凸起，使得在I / O焊盘上的相关的抗裂结构上形成焊料凸块。

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