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1. 发明授权

US07800450B2 Re-configurable low noise amplifier utilizing feedback capacitors 有权
标题翻译：利用反馈电容器重新配置低噪声放大器
公开(公告)号：US07800450B2
公开(公告)日：2010-09-21
申请号：US12358419
申请日：2009-01-23
申请人： Jae-woo Park , Chang-sik Yoo
发明人： Jae-woo Park , Chang-sik Yoo
IPC分类号： H03F3/68
CPC分类号： H03F3/193 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/378 , H03F2200/387 , H03F2200/429 , H03F2200/451
摘要： A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output portion. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input portion of the low noise amplifier for input matching. Since the output portion is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure.
摘要翻译：公开了一种利用反馈电容器的可重构低噪声放大器。低噪声放大器具有输出晶体管，电容开关单元和电容分配器。输出晶体管用于控制宽频带中的特定频带的选择。电容开关单元用于调整特定频带的谐波频率。电容分配器用于确定增益量，并且根据增益，输出阻抗反馈到低噪声放大器的输入部分用于输入匹配。由于输出部分处于高阻抗并且适用于宽频带，输入匹配不仅使低噪声放大器适用于各种无线通信标准，而且还实现了高增益和低噪声系数。

2. 发明申请

US20080113682A1 COMMUNICATION APPARATUS AND LOW NOISE AMPLIFYING METHOD 有权
标题翻译：通信装置和低噪声放大方法
公开(公告)号：US20080113682A1
公开(公告)日：2008-05-15
申请号：US11733401
申请日：2007-04-10
申请人： Jae-woo PARK , Chang-sik Yoo , Jin-soo Park , Heung-bae Lee , Young-eil Kim
发明人： Jae-woo PARK , Chang-sik Yoo , Jin-soo Park , Heung-bae Lee , Young-eil Kim
IPC分类号： H04B7/00
CPC分类号： H03G3/3036
摘要： A communication apparatus and a low noise amplifying method. The communication apparatus includes a gain adjusting unit to adjust a gain of an input signal; a combiner to generate an output signal using the signal gain-adjusted at the gain adjusting unit; and a feedback unit which provides a feedback signal, which is generated using the output signal generated at the combiner, to an input stage. Accordingly, various frequency bands defined in the wireless standards can be supported. Since the load impedance is generated without resistance, the manufacturing cost and the product size can be reduced.
摘要翻译：通信装置和低噪声放大方法。通信装置包括：增益调整单元，用于调节输入信号的增益; 组合器，用于使用在增益调整单元处调整的信号增益来产生输出信号; 以及反馈单元，其将使用在组合器处产生的输出信号生成的反馈信号提供给输入级。因此，可以支持在无线标准中定义的各种频带。由于无阻力地产生负载阻抗，因此可以降低制造成本和产品尺寸。

3. 发明授权

US08078126B2 Communication apparatus and low noise amplifying method 有权
标题翻译：通信设备和低噪声放大方法
公开(公告)号：US08078126B2
公开(公告)日：2011-12-13
申请号：US11733401
申请日：2007-04-10
申请人： Jae-woo Park , Chang-sik Yoo , Jin-soo Park , Heung-bae Lee , Young-eil Kim
发明人： Jae-woo Park , Chang-sik Yoo , Jin-soo Park , Heung-bae Lee , Young-eil Kim
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03G3/3036
摘要： A communication apparatus and a low noise amplifying method. The communication apparatus includes a gain adjusting unit to adjust a gain of an input signal; a combiner to generate an output signal using the signal gain-adjusted at the gain adjusting unit; and a feedback unit which provides a feedback signal, which is generated using the output signal generated at the combiner, to an input stage. Accordingly, various frequency bands defined in the wireless standards can be supported. Since the load impedance is generated without resistance, the manufacturing cost and the product size can be reduced.
摘要翻译：通信装置和低噪声放大方法。通信装置包括：增益调整单元，用于调节输入信号的增益; 组合器，用于使用在增益调整单元处调整的信号增益来产生输出信号; 以及反馈单元，其将使用在组合器处产生的输出信号生成的反馈信号提供给输入级。因此，可以支持在无线标准中定义的各种频带。由于无阻力地产生负载阻抗，因此可以降低制造成本和产品尺寸。

4. 发明申请

US20090195316A1 RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS 有权
标题翻译：可重新配置低噪声放大器，利用反馈电容器
公开(公告)号：US20090195316A1
公开(公告)日：2009-08-06
申请号：US12358419
申请日：2009-01-23
申请人： Jae-woo Park , Chang-sik Yoo
发明人： Jae-woo Park , Chang-sik Yoo
IPC分类号： H03F3/16
CPC分类号： H03F3/193 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/378 , H03F2200/387 , H03F2200/429 , H03F2200/451
摘要： A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure.
摘要翻译：公开了一种利用反馈电容器的可重构低噪声放大器。低噪声放大器具有输出晶体管，电容开关单元和电容分配器。输出晶体管用于控制宽频带中的特定频带的选择。电容开关单元用于调整特定频带的谐波频率。电容分配器用于确定增益量，并且根据增益，输出阻抗反馈到低噪声放大器的输入端以进行输入匹配。由于输出端子处于高阻抗并且适用于宽频带，所以输入匹配不仅可以使低噪声放大器适用于各种无线通信标准，而且可以实现高增益和低噪声系数。

5. 发明授权

US07804720B2 Integrated circuit memory devices including mode registers set using a data input/output bus 有权
标题翻译：集成电路存储器件包括使用数据输入/输出总线设置的模式寄存器
公开(公告)号：US07804720B2
公开(公告)日：2010-09-28
申请号：US12614826
申请日：2009-11-09
申请人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
发明人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
IPC分类号： G11C7/10
CPC分类号： G11C5/00 , G11C5/04 , G11C7/10 , G11C7/1045 , G11C7/222 , G11C8/06 , G11C8/10 , G11C11/4076 , G11C11/4093
摘要： An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.
摘要翻译：集成电路存储器件可以包括存储单元阵列和多个数据输入/输出引脚。多个数据输入/输出引脚可以被配置为在数据写入操作期间从存储器控制器接收要写入存储单元阵列的数据，并且数据输入/输出引脚还可以被配置为向存储器控制器在数据读取操作期间从存储单元阵列。模式寄存器可以被配置为存储定义存储器件的操作特性的信息，并且模式寄存器可以被配置为使用数据输入/输出总线进行设置。还讨论了相关方法，系统和附加设备。

6. 发明授权

US07636273B2 Integrated circuit memory devices that support selective mode register set commands 有权
标题翻译：支持选择性模式寄存器设置命令的集成电路存储器件
公开(公告)号：US07636273B2
公开(公告)日：2009-12-22
申请号：US12260373
申请日：2008-10-29
申请人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
发明人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C5/04 , G11C7/10 , G11C7/1045 , G11C7/222 , G11C8/06 , G11C8/10 , G11C11/4076 , G11C11/4093
摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.
摘要翻译：存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现存储器件在模式寄存器设置操作期间。可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令存储器件在模式寄存器设置操作期间。此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。还讨论了相关系统，设备和附加方法。

7. 发明申请

US20080175071A1 Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes 审中-公开
标题翻译：操作内存系统的方法，包括设置为不同操作模式的内存设备
公开(公告)号：US20080175071A1
公开(公告)日：2008-07-24
申请号：US12058441
申请日：2008-03-28
申请人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
发明人： Kee-hoon Lee , Chang-sik Yoo , Kye-hyun Kyung
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G06F13/1694 , G11C7/10 , G11C7/1045 , G11C11/4093
摘要： A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.
摘要翻译：可以提供一种操作包括耦合到命令地址总线的多个存储器件的存储器系统的方法。特别地，多个存储器件的第一存储器件可以被设置为第一操作模式，并且多个存储器件中的第二存储器件可以被设置为与第一操作模式不同的第二操作模式。此外，可以响应于通过命令地址总线提供给多个存储器件的读/写命令地址信号执行读/写操作，使得第一存储器件在读/写期间根据第一操作模式进行操作并且使得第二存储器件在读/写操作期间根据第二操作模式操作。还讨论了相关系统。

8. 发明申请

US20060181356A1 Quadrature voltage controlled oscillator 有权
标题翻译：正交压控振荡器
公开(公告)号：US20060181356A1
公开(公告)日：2006-08-17
申请号：US11348229
申请日：2006-02-07
申请人： Jin-soo Park , Chan-young Jeong , Chang-sik Yoo , Seong-soo Lee , Heung-bae Lee
发明人： Jin-soo Park , Chan-young Jeong , Chang-sik Yoo , Seong-soo Lee , Heung-bae Lee
IPC分类号： H03B27/00
CPC分类号： H03B27/00 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B2200/0078
摘要： A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.
摘要翻译：具有低相位噪声和优异输出摆幅特性的正交压控振荡器包括用于输出正同相输出信号和负同相输出信号的第一压控振荡器; 用于输出正正交相输出信号和负正交相输出信号的第二压控振荡器，所述第二压控振荡器与所述第一压控振荡器具有对称结构，并与所述第一压控振荡器一起构成反馈回路 ; 用于响应于所述输出信号向所述第一压控振荡器提供恒定电流的第一恒流源; 以及用于响应于输出信号向第二压控振荡器提供恒定电流的第二恒流源。

9. 发明授权

US06834014B2 Semiconductor memory systems, methods, and devices for controlling active termination 有权
标题翻译：用于控制有源终端的半导体存储器系统，方法和装置
公开(公告)号：US06834014B2
公开(公告)日：2004-12-21
申请号：US10199857
申请日：2002-07-19
申请人： Chang-sik Yoo , Kye-hyun Kyung
发明人： Chang-sik Yoo , Kye-hyun Kyung
IPC分类号： G11C1604
CPC分类号： G11C7/1066 , G11C7/10 , G11C7/1045 , G11C11/4093
摘要： An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. The memory device also includes at least one switch coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage wherein the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off. Related memory systems and methods are also discussed.
摘要翻译：用于存储器系统的集成电路存储器装置从存储器控制器接收预定的命令/地址信号，并响应于命令/地址信号读取和写入数据。存储器件包括至少一个输入/输出端子，其通过数据输入/输出总线，至少一个终端电阻器和产生控制信号的有源终端控制信号发生器来输入/输出数据到存储器控制器响应于来自存储器控制器的芯片选择信号，主动终止至少一个数据输入/输出终端。存储器件还包括至少一个开关，其与至少一个输入/输出端子与预定电压之间的至少一个终端电阻器串联耦合，其中至少一个开关响应于控制信号而被接通/断开所述至少一个输入/输出端子响应于所述控制信号而与所述预定电压连接/断开，并且使得所述至少一个终端电阻串联在所述预定电压和所述至少一个输入/输出端子之间当所述至少一个开关被接通时，并且当所述至少一个开关被切断时，所述至少一个输入/输出端与所述预定电压分离。还讨论了相关的内存系统和方法。

10. 发明授权

US06603686B2 Semiconductor memory device having different data rates in read operation and write operation 失效
公开(公告)号：US06603686B2
公开(公告)日：2003-08-05
申请号：US10246744
申请日：2002-09-19
申请人： Chang-sik Yoo , Tae-sung Jung
发明人： Chang-sik Yoo , Tae-sung Jung
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1051
摘要： A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

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