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1. 发明授权

US06477110B2 Semiconductor memory device having different data rates in read operation and write operation 失效
标题翻译：在读取操作和写入操作中具有不同数据速率的半导体存储器件
公开(公告)号：US06477110B2
公开(公告)日：2002-11-05
申请号：US09930973
申请日：2001-08-17
申请人： Chang-sik Yoo , Tae-sung Jung
发明人： Chang-sik Yoo , Tae-sung Jung
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1051
摘要： A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.
摘要翻译：半导体存储器件和使用半导体存储器件的系统可以安全地执行数据采样操作，而不需要诸如延迟锁定环（DLL）或锁相环（PLL）的相位同步装置，其中半导体存储器件包括选通信号，其与数据信号同步，两者遍历存储器件和存储器控制器之间的相似长度的路径。在读取操作中，半导体存储器件产生与读取数据信号同步的第一选通信号，从而在选通信号的上升沿和下降沿都输出读取数据信号。在写入操作中，产生第二选通信号，由此仅使用单个边沿来产生写数据信号，从而允许发生足够的时间进行数据采样操作，从而以读操作的一半的速度运行。

2. 发明授权

US06603686B2 Semiconductor memory device having different data rates in read operation and write operation 失效
公开(公告)号：US06603686B2
公开(公告)日：2003-08-05
申请号：US10246744
申请日：2002-09-19
申请人： Chang-sik Yoo , Tae-sung Jung
发明人： Chang-sik Yoo , Tae-sung Jung
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1051
摘要： A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

3. 发明授权

US07246250B2 Memory device controls delay time of data input buffer in response to delay control information based on a position of a memory device received from memory controller 失效
标题翻译：存储器件响应于基于从存储器控制器接收的存储器件的位置的延迟控制信息来控制数据输入缓冲器的延迟时间
公开(公告)号：US07246250B2
公开(公告)日：2007-07-17
申请号：US09941091
申请日：2001-08-28
申请人： Tae-sung Jung , Won-ki Song
发明人： Tae-sung Jung , Won-ki Song
IPC分类号： G06F1/12
CPC分类号： G11C7/109 , G06F13/1689 , G11C7/1078 , G11C7/1084
摘要： An integrated circuit memory system includes one or more memory modules in which at least one of the memory modules is responsive to a control signal and has delay control information stored thereon. The memory system further includes a memory controller that is configured to generate the control signal in response to the delay control information.
摘要翻译：集成电路存储器系统包括一个或多个存储器模块，其中至少一个存储器模块响应于控制信号并且具有存储在其上的延迟控制信息。存储器系统还包括存储器控制器，其被配置为响应于延迟控制信息而产生控制信号。

4. 发明授权

US07334137B2 Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller 有权
标题翻译：将存储器耦合到存储器控制器并且响应于与存储器和存储器控制器的电源电压无关的端子电压的存储器接口系统
公开(公告)号：US07334137B2
公开(公告)日：2008-02-19
申请号：US09851277
申请日：2001-05-08
申请人： Tae-sung Jung , Byung-se So , Myun-joo Park
发明人： Tae-sung Jung , Byung-se So , Myun-joo Park
IPC分类号： G06F1/00 , G11C7/00 , G11C7/02 , H02J1/10 , H02J1/00
CPC分类号： G11C7/1084 , G06F13/1668 , G06F13/4086 , G11C7/1078 , Y10T307/383 , Y10T307/658 , Y10T307/669 , Y10T307/675
摘要： Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the memory interface system uses a terminal voltage that is independent of the supply voltages of the memory and the memory controller, the interface system may be unaffected by voltage differences between the memory supply voltage and the memory controller supply voltage.
摘要翻译：存储器接口系统包括将存储器耦合到存储器控制器的一个或多个通道线，使得通道线响应于独立于存储器和存储器控制器的电源电压的端子电压。因为存储器接口系统使用独立于存储器和存储器控制器的电源电压的端子电压，所以接口系统可以不受存储器电源电压和存储器控制器电源电压之间的电压差的影响。

5. 发明授权

US06585525B2 Memory modules having conductors at edges thereof and configured to conduct signals to or from the memory modules via the respective edges 失效
标题翻译：存储器模块在其边缘处具有导体并且被配置为经由相应的边缘向存储器模块或从存储器模块传送信号
公开(公告)号：US06585525B2
公开(公告)日：2003-07-01
申请号：US09845550
申请日：2001-04-30
申请人： Tae-sung Jung , Won-ki Song
发明人： Tae-sung Jung , Won-ki Song
IPC分类号： H01R1200
CPC分类号： G11C5/06 , G11C5/04 , H05K1/142
摘要： Memory modules, and related memory module sockets, can include a plurality of connector pins adjacent to a first edge of the memory module that are configured to conduct a plurality of first signals to or from the memory module via the first edge and a plurality of first conductors adjacent to a second edge of the memory module that are configured to conduct a plurality of second signals to or from the memory module via the second edge.
摘要翻译：存储器模块和相关存储器模块插槽可以包括与存储器模块的第一边缘相邻的多个连接器引脚，其被配置为经由第一边缘和/或从存储器模块经由第一边缘向存储器模块或从存储器模块传导多个第一信号，与存储器模块的第二边缘相邻的导体，其被配置为经由第二边缘向存储器模块或从存储器模块传导多个第二信号。

6. 发明授权

US06442057B1 Memory module for preventing skew between bus lines 有权
公开(公告)号：US06442057B1
公开(公告)日：2002-08-27
申请号：US09886552
申请日：2001-06-21
申请人： Won-ki Song , Tae-sung Jung
发明人： Won-ki Song , Tae-sung Jung
IPC分类号： G11C506
CPC分类号： H05K1/0248 , G06F13/4234 , G11C5/063 , H05K2201/09254 , H05K2201/10159
摘要： A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.

7. 发明授权

US06275100B1 Reference voltage generators including first and second transistors of same conductivity type and at least one switch 失效
标题翻译：参考电压发生器包括具有相同导电类型的第一和第二晶体管和至少一个开关
公开(公告)号：US06275100B1
公开(公告)日：2001-08-14
申请号：US09514763
申请日：2000-02-28
申请人： Jong-min Park , Tae-sung Jung
发明人： Jong-min Park , Tae-sung Jung
IPC分类号： G05F110
CPC分类号： G05F3/247
摘要： Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply voltages, such that the first transistor operates below the threshold voltage thereof and the second transistor operates above the threshold voltage thereof. The first transistor includes a gate that is coupled to a first node connected to a first power supply voltage and that is connected between an output reference voltage terminal and a second node that is connected to a second power supply voltage. The second transistor includes a gate that is coupled to the second node and is connected between the first node and the second power supply voltage. At least one switch also may be included, which disconnects the reference voltage generator from the first and second power supply voltages in response to a control signal, to thereby allow reduced standby power.
摘要翻译：通过提供相互连接的第一和第二电源类型的第一和第二晶体管以及在第一和第二电源电压之间，使得第一晶体管工作，参考电压发生器可以由于器件制造过程而对阈值电压的变化相对不敏感低于其阈值电压，而第二晶体管工作在其阈值电压之上。第一晶体管包括耦合到连接到第一电源电压的第一节点并且连接在输出参考电压端子和连接到第二电源电压的第二节点之间的栅极。第二晶体管包括耦合到第二节点并连接在第一节点和第二电源电压之间的栅极。还可以包括至少一个开关，其响应于控制信号将参考电压发生器与第一和第二电源电压断开，从而允许减少的待机功率。

8. 发明授权

US6040735A Reference voltage generators including first and second transistors of same conductivity type 失效
标题翻译：参考电压发生器包括具有相同导电类型的第一和第二晶体管
公开(公告)号：US6040735A
公开(公告)日：2000-03-21
申请号：US927606
申请日：1997-09-12
申请人： Jong-min Park , Tae-sung Jung
发明人： Jong-min Park , Tae-sung Jung
IPC分类号： G11C11/413 , G05F3/24 , G11C5/14 , G11C11/407 , H01L21/822 , H01L27/04 , H03K19/00 , G05F1/10
CPC分类号： G05F3/247
摘要： Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply voltages, such that the first transistor operates below the threshold voltage thereof and the second transistor operates above the threshold voltage thereof. The first transistor includes a gate that is coupled to a first node connected to a first power supply voltage and that is connected between an output reference voltage terminal and a second node that is connected to a second power supply voltage. The second transistor includes a gate that is coupled to the second node and is connected between the first node and the second power supply voltage.
摘要翻译：通过提供相互连接的第一和第二电源类型的第一和第二晶体管以及在第一和第二电源电压之间，使得第一晶体管工作，参考电压发生器可以由于器件制造过程而对阈值电压的变化相对不敏感低于其阈值电压，而第二晶体管工作在其阈值电压之上。第一晶体管包括耦合到连接到第一电源电压的第一节点并且连接在输出参考电压端子和连接到第二电源电压的第二节点之间的栅极。第二晶体管包括耦合到第二节点并连接在第一节点和第二电源电压之间的栅极。

9. 发明授权

US6044017A Flash memory device 失效
标题翻译：闪存设备
公开(公告)号：US6044017A
公开(公告)日：2000-03-28
申请号：US82297
申请日：1998-05-19
申请人： Dong-gi Lee , Tae-sung Jung
发明人： Dong-gi Lee , Tae-sung Jung
IPC分类号： G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , C11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A flash memory includes an array of memory cells having sources, drains, floating gates, and control gates. The array includes a conductive plate formed over the memory cells to affect a capacitive coupling between the memory cells and the conductive plate. A first voltage source provides a first voltage to the control gate of a selected one of the memory cells. A second voltage source provides a second voltage to the conductive plate after the control gate of the selected one of the memory cells has been charged up to a predetermined voltage level. Additionally, the flash memory includes a switching circuit to transfer the first and second voltages to the control gate of the selected memory cell and the conductive plate, respectively, responsive to a first and second control signals.
摘要翻译：闪速存储器包括具有源极，漏极，浮动栅极和控制栅极的存储器单元阵列。阵列包括形成在存储器单元上的导电板，以影响存储器单元和导电板之间的电容耦合。第一电压源向所选存储器单元的控制栅极提供第一电压。在所选择的一个存储单元的控制栅极已经被充电到预定电压电平之后，第二电压源向导电板提供第二电压。此外，闪速存储器包括切换电路，用于分别响应于第一和第二控制信号将第一和第二电压传送到所选择的存储单元和导电板的控制栅极。

10. 发明授权

US5761123A Sense amplifier circuit of a nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的感测放大器电路
公开(公告)号：US5761123A
公开(公告)日：1998-06-02
申请号：US663350
申请日：1996-06-13
申请人： Myung-jae Kim , Tae-sung Jung
发明人： Myung-jae Kim , Tae-sung Jung
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06 , G11C7/00
CPC分类号： G11C7/065
摘要： A sense amplifier circuit for a nonvolatile semiconductor memory device, with NAND structured cells, includes a bit line isolation section located between a pair of bit lines connected to a memory cell array and a pair of sub-bit lines connected to an input/output gate circuit, a latch type voltage-controlled current source having n-channel MOS transistors connected to the sub-bit lines, and a switching section connected between the voltage-controlled current source and a signal line. The bit lines are electrically isolated from the sub-bit lines by provision of a bit line isolation section receiving an isolation control signal during the sensing operation. The sense amplifier circuit sensing operation is not affected by bit line load impedance and, accordingly, the sensing speed is improved and peak current is reduced.
摘要翻译：一种用于具有NAND结构单元的非易失性半导体存储器件的读出放大器电路，包括位线隔离部分，位于连接到存储单元阵列的一对位线和连接到输入/输出门的一对子位线之间电路，具有连接到子位线的n沟道MOS晶体管的锁存型压控电流源，以及连接在压控电流源与信号线之间的开关部。通过提供在感测操作期间接收隔离控制信号的位线隔离部分，位线与子位线电隔离。感测放大器电路感测操作不受位线负载阻抗的影响，因此感测速度提高，峰值电流降低。

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