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1. 发明申请

US20050184348A1 Semiconductor device gate structure and method of forming the same 审中-公开
标题翻译：半导体器件栅极结构及其形成方法
公开(公告)号：US20050184348A1
公开(公告)日：2005-08-25
申请号：US11059145
申请日：2005-02-15
申请人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
发明人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/823487 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
摘要翻译：公开了一种MOS晶体管，其包括在垂直方向上延伸半导体衬底的栅极结构。栅极结构包括从垂直方向从衬底延伸的栅极电极和围绕栅电极的栅极绝缘层。沟道图案包围栅极绝缘层，并且第一导电图案沿着垂直于沟道图案的第一方向并且与衬底平行地从沟道图案的下部延伸。第二导电图案沿着垂直于沟道图案的第二方向并与衬底平行地从沟道图案的上部延伸。因此，MOS晶体管的沟道长度由第一和第二导电图案之间的距离决定，并且MOS晶体管的沟道宽度由栅极结构的直径决定。在MOS晶体管中充分防止了短沟道和窄宽度效应。

2. 发明授权

US07317230B2 Fin FET structure 有权
标题翻译：翅片FET结构
公开(公告)号：US07317230B2
公开(公告)日：2008-01-08
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

3. 发明申请

US20050173768A1 Fin fet structure 有权
标题翻译：鳍结构
公开(公告)号：US20050173768A1
公开(公告)日：2005-08-11
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L29/49 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

4. 发明申请

US20050056888A1 Double gate field effect transistor and method of manufacturing the same 失效
标题翻译：双栅场效应晶体管及其制造方法
公开(公告)号：US20050056888A1
公开(公告)日：2005-03-17
申请号：US10917026
申请日：2004-08-11
申请人： Jae-Man Youn , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
发明人： Jae-Man Youn , Dong-gun Park , Gyo-young Jin , Yoshida Makoto , Tai-su Park
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/7851 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.
摘要翻译：提供双栅场效应晶体管及其制造方法。制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

5. 发明授权

US07279774B2 Bulk substrates in FinFETs with trench insulation surrounding FIN pairs having FINs separated by recess hole shallower than trench 失效
标题翻译： FinFET中的散装衬底，具有沟槽绝缘体，其周围具有FIN对，其具有通过比沟槽浅的凹槽分隔的FIN
公开(公告)号：US07279774B2
公开(公告)日：2007-10-09
申请号：US10938436
申请日：2004-09-09
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Youn
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Youn
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.
摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。栅极线形成为覆盖并延伸穿过通道散热片。源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。描述和要求保护其他实施例。

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