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1. 发明申请

US20050184348A1 Semiconductor device gate structure and method of forming the same 审中-公开
标题翻译：半导体器件栅极结构及其形成方法
公开(公告)号：US20050184348A1
公开(公告)日：2005-08-25
申请号：US11059145
申请日：2005-02-15
申请人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
发明人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/823487 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
摘要翻译：公开了一种MOS晶体管，其包括在垂直方向上延伸半导体衬底的栅极结构。栅极结构包括从垂直方向从衬底延伸的栅极电极和围绕栅电极的栅极绝缘层。沟道图案包围栅极绝缘层，并且第一导电图案沿着垂直于沟道图案的第一方向并且与衬底平行地从沟道图案的下部延伸。第二导电图案沿着垂直于沟道图案的第二方向并与衬底平行地从沟道图案的上部延伸。因此，MOS晶体管的沟道长度由第一和第二导电图案之间的距离决定，并且MOS晶体管的沟道宽度由栅极结构的直径决定。在MOS晶体管中充分防止了短沟道和窄宽度效应。

2. 发明申请

US20050173768A1 Fin fet structure 有权
标题翻译：鳍结构
公开(公告)号：US20050173768A1
公开(公告)日：2005-08-11
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L29/49 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

3. 发明授权

US07317230B2 Fin FET structure 有权
标题翻译：翅片FET结构
公开(公告)号：US07317230B2
公开(公告)日：2008-01-08
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

4. 发明授权

US07919378B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07919378B2
公开(公告)日：2011-04-05
申请号：US12397176
申请日：2009-03-03
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

5. 发明申请

US20050176186A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050176186A1
公开(公告)日：2005-08-11
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

6. 发明授权

US07323375B2 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US07323375B2
公开(公告)日：2008-01-29
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

7. 发明申请

US20050250285A1 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US20050250285A1
公开(公告)日：2005-11-10
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/786 , H01L29/94
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

8. 发明授权

US07579648B2 Semiconductor device having a channel pattern and method of manufacturing the same 有权
标题翻译：具有沟道图案的半导体器件及其制造方法
公开(公告)号：US07579648B2
公开(公告)日：2009-08-25
申请号：US11183997
申请日：2005-07-19
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/78696 , H01L29/66666 , H01L29/66772 , H01L29/78642
摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.
摘要翻译：半导体器件可以包括从半导体衬底垂直延伸的管状沟道图案。可以在通过通道图案暴露的面上设置栅极绝缘层。栅极电极可以设置在栅极绝缘层上。栅电极可以填充沟道图案。可以在半导体衬底的表面部分处形成可用作下部源极/漏极区域的导电区域。导电区域可以接触通道图案的下部。可以用作上部源极/漏极区域的导电图案可以从沟道图案的上部部分水平延伸。

9. 发明申请

US20080293203A1 Semiconductor device having a fin structure and method of manufacturing the same 失效
标题翻译：具有翅片结构的半导体器件及其制造方法
公开(公告)号：US20080293203A1
公开(公告)日：2008-11-27
申请号：US12219984
申请日：2008-07-31
申请人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
发明人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
摘要翻译：半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。栅极绝缘层可以设置在通道散热片上。栅电极可以包括下栅极图案和上栅极图案。下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。上栅极图案可以连接到下栅极图案的上部。

10. 发明授权

US07420244B2 Semiconductor device having a fin structure and method of manufacturing the same 失效
公开(公告)号：US07420244B2
公开(公告)日：2008-09-02
申请号：US11183995
申请日：2005-07-19
申请人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
发明人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

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