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1. 发明申请

US20110205217A1 METHOD OF DRIVING DISPLAY PANEL 有权
标题翻译：驱动显示面板的方法
公开(公告)号：US20110205217A1
公开(公告)日：2011-08-25
申请号：US12451066
申请日：2008-04-24
申请人： Jae-Gun Park , Gon-Sub Lee , Su-Hwan Lee , Sung-Ho Seo , Dong-Won Shin , Dal-Ho Kim , Hyun-Min Seung
发明人： Jae-Gun Park , Gon-Sub Lee , Su-Hwan Lee , Sung-Ho Seo , Dong-Won Shin , Dal-Ho Kim , Hyun-Min Seung
IPC分类号： G09G5/00 , G09G3/30
CPC分类号： H05B33/22 , B82Y20/00 , B82Y30/00 , G09G3/2011 , G09G3/3216 , G09G2310/061 , H01L27/26 , H01L27/3244 , H01L51/0591 , H01L51/52 , H01L2251/5338 , H01L2251/5369
摘要： Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.
摘要翻译：提供了一种驱动具有电荷捕获器件和有机发光二极管（OLED）的显示面板的方法。电荷捕获器件包括纳米晶体层。纳米晶体层包括结晶和分散的纳米晶体，以及掩埋纳米晶体的阻挡层。当施加编程电压时，电荷被捕获在纳米晶体中，并且OLED通过施加读取电压以预定亮度发光。数据信号顺序地施加到显示面板的所有像素以表达所需的灰度。显示面板的像素接收读取电压并同时发光。

2. 发明授权

US08441472B2 Method of driving display panel 有权
标题翻译：显示面板驱动方法
公开(公告)号：US08441472B2
公开(公告)日：2013-05-14
申请号：US12451066
申请日：2008-04-24
申请人： Jae-Gun Park , Gon-Sub Lee , Su-Hwan Lee , Sung-Ho Seo , Woo-Sik Nam , Dong-Won Shin , Dal-Ho Kim , Hyun-Min Seung , Jong-Dae Lee
发明人： Jae-Gun Park , Gon-Sub Lee , Su-Hwan Lee , Sung-Ho Seo , Woo-Sik Nam , Dong-Won Shin , Dal-Ho Kim , Hyun-Min Seung , Jong-Dae Lee
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： H05B33/22 , B82Y20/00 , B82Y30/00 , G09G3/2011 , G09G3/3216 , G09G2310/061 , H01L27/26 , H01L27/3244 , H01L51/0591 , H01L51/52 , H01L2251/5338 , H01L2251/5369
摘要： Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.
摘要翻译：提供了一种驱动具有电荷捕获器件和有机发光二极管（OLED）的显示面板的方法。电荷捕获器件包括纳米晶体层。纳米晶体层包括结晶和分散的纳米晶体，以及掩埋纳米晶体的阻挡层。当施加编程电压时，电荷被捕获在纳米晶体中，并且OLED通过施加读取电压以预定亮度发光。数据信号顺序地施加到显示面板的所有像素以表达所需的灰度。显示面板的像素接收读取电压并同时发光。

3. 发明申请

US20110127580A1 CAPACITOR-LESS MEMORY DEVICE 有权
标题翻译：无电容器存储器件
公开(公告)号：US20110127580A1
公开(公告)日：2011-06-02
申请号：US12990353
申请日：2009-04-30
申请人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
发明人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
IPC分类号： H01L29/772
CPC分类号： H01L29/4234 , G11C11/404 , G11C16/0466 , G11C2211/4016 , H01L27/10802 , H01L29/7841 , H01L29/78687 , H01L29/78696
摘要： Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
摘要翻译：提供了一种无电容器存储器件。所述器件包括半导体衬底，设置在所述半导体衬底上的绝缘层，设置在所述绝缘层的部分区域上的存储区域，设置在所述存储区域上以在所述沟道区域和所述沟道区域之间提供价带能量偏移的沟道区域顺序地设置在沟道区上的栅极绝缘层和栅电极以及连接到沟道区并设置在栅电极两侧的源极和漏极区。在通道区域单元的下方配置具有与通道区域不同的价带能量的存储区域，使得捕获在存储区域单元中的电荷不容易排出。因此，可以增加电荷保留时间以提高数据存储能力。

4. 发明申请

US20080305574A1 METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE USING CONDUCTIVE ORGANIC POLYMER HAVING NANOCRYSTALS EMBEDDED THEREIN 审中-公开
标题翻译：使用具有嵌入的纳米晶体的导电有机聚合物制造非易失性存储器件的方法
公开(公告)号：US20080305574A1
公开(公告)日：2008-12-11
申请号：US12108612
申请日：2008-04-24
申请人： Jea-Gun Park , Gon-Sub Lee , Byeong-Il Han , Jong-Dae Lee
发明人： Jea-Gun Park , Gon-Sub Lee , Byeong-Il Han , Jong-Dae Lee
IPC分类号： H01L51/30
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2211/5614 , H01L51/0042 , H01L51/0591
摘要： The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive organic layer; forming a second conductive organic layer on the first conductive organic layer using spin coating; transforming the metal layer into nanocrystals by curing; and forming an upper conductive layer on the second conductive organic layer, the upper conductive layer partially overlapping the nanocrystals. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS).
摘要翻译：非易失性存储器件的制造方法包括在基板上形成下导电层; 使用旋涂在所述基板上形成第一导电有机层; 在所述第一导电有机层上形成用于形成纳米晶体的金属层，所述金属层与所述第一导电有机层部分重叠; 使用旋涂在所述第一导电有机层上形成第二导电有机层; 通过固化将金属层转化为纳米晶体; 以及在所述第二导电有机层上形成上导电层，所述上导电层部分地与所述纳米晶体重叠。导电有机聚合物可以是聚-N-乙烯基咔唑（PVK）或聚苯乙烯（PS）。

5. 发明授权

US07338882B2 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same 有权
标题翻译：制造纳米SOI晶片和纳米SOI晶片的方法
公开(公告)号：US07338882B2
公开(公告)日：2008-03-04
申请号：US11084033
申请日：2005-03-21
申请人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
发明人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
IPC分类号： H01L21/46 , H01L21/302
CPC分类号： H01L21/76254 , Y10S438/959
摘要： A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.
摘要翻译：提供了不进行化学机械抛光（CMP）和由其制造的晶片的制造具有优异的厚度均匀性的纳米绝缘体（SOI）晶片的方法。所提供的方法包括制备接合晶片和基底晶片，并且在接合晶片的至少一个表面上形成电介质。此后，通过以低电压将杂质离子注入接合晶片到接合晶片的表面至预定深度来形成杂质离子注入单元。接合晶片和基底晶片的电介质彼此接触以便结合。接下来，进行低温的热处理，以切割接合晶片的杂质离子注入单元。此外，蚀刻结合到基底晶片的接合晶片的切割表面以形成纳米级器件区域。这里，可以通过进行氢表面处理和湿蚀刻来蚀刻裂开的表面。

6. 发明申请

US20050164435A1 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same 有权
标题翻译：制造纳米SOI晶片和纳米SOI晶片的方法
公开(公告)号：US20050164435A1
公开(公告)日：2005-07-28
申请号：US11084033
申请日：2005-03-21
申请人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
发明人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
IPC分类号： H01L21/20 , H01L21/02 , H01L21/265 , H01L21/762 , H01L27/12 , H01L21/00 , H01L21/30 , H01L21/46 , H01L21/84
CPC分类号： H01L21/76254 , Y10S438/959
摘要： A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.
摘要翻译：提供了不进行化学机械抛光（CMP）和由其制造的晶片的制造具有优异的厚度均匀性的纳米绝缘体（SOI）晶片的方法。所提供的方法包括制备接合晶片和基底晶片，并且在接合晶片的至少一个表面上形成电介质。此后，通过以低电压将杂质离子注入接合晶片到接合晶片的表面至预定深度来形成杂质离子注入单元。接合晶片和基底晶片的电介质彼此接触以便结合。接下来，进行低温的热处理，以切割接合晶片的杂质离子注入单元。此外，蚀刻结合到基底晶片的接合晶片的切割表面以形成纳米级器件区域。这里，可以通过进行氢表面处理和湿蚀刻来蚀刻裂开的表面。

7. 发明授权

US08860109B2 Capacitor-less memory device 有权
标题翻译：无电容存储器件
公开(公告)号：US08860109B2
公开(公告)日：2014-10-14
申请号：US12990353
申请日：2009-04-30
申请人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
发明人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
IPC分类号： H01L27/108 , H01L29/78 , G11C11/404 , H01L29/423 , G11C16/04 , H01L29/786
CPC分类号： H01L29/4234 , G11C11/404 , G11C16/0466 , G11C2211/4016 , H01L27/10802 , H01L29/7841 , H01L29/78687 , H01L29/78696
摘要： Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
摘要翻译：提供了一种无电容器存储器件。所述器件包括半导体衬底，设置在所述半导体衬底上的绝缘层，设置在所述绝缘层的部分区域上的存储区域，设置在所述存储区域上以在所述沟道区域和所述沟道区域之间提供价带能量偏移的沟道区域顺序地设置在沟道区上的栅极绝缘层和栅电极以及连接到沟道区并设置在栅电极两侧的源极和漏极区。在通道区域单元的下方配置具有与通道区域不同的价带能量的存储区域，使得捕获在存储区域单元中的电荷不容易排出。因此，可以增加电荷保留时间以提高数据存储能力。

8. 发明授权

US06884694B2 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same 有权
公开(公告)号：US06884694B2
公开(公告)日：2005-04-26
申请号：US10391297
申请日：2003-03-19
申请人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
发明人： Jea-Gun Park , Gon-Sub Lee , Sang-Hee Lee
IPC分类号： H01L21/20 , H01L21/02 , H01L21/265 , H01L21/762 , H01L27/12 , H01L21/30
CPC分类号： H01L21/76254 , Y10S438/959
摘要： A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

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