专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120072743A1 Hierarchical Power Management Circuit, Power Management Method Using the Same, and System on Chip Including the Hierarchical Power Management Circuit 有权
标题翻译：分层电源管理电路，使用该电路的电源管理方法，以及包括分层电源管理电路的片上系统
公开(公告)号：US20120072743A1
公开(公告)日：2012-03-22
申请号：US13233841
申请日：2011-09-15
申请人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
发明人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , Y02D10/171
摘要： A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1
摘要翻译：分级电源管理电路包括分别包括在N个电源域中的N个电源管理电路，每个电源域包括至少一个知识产权（IP），其中N是大于1的自然数。来自N个电力管理电路的第i（1

2. 发明授权

US09268395B2 Hierarchical power management circuit, power management method using the same, and system on chip including the hierarchical power management circuit 有权
标题翻译：分层电源管理电路，使用其电源管理方法，以及片上系统包括分层电源管理电路
公开(公告)号：US09268395B2
公开(公告)日：2016-02-23
申请号：US13233841
申请日：2011-09-15
申请人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
发明人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , Y02D10/171
摘要： A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1
摘要翻译：分级电源管理电路包括分别包括在N个电源域中的N个电源管理电路，每个电源域包括至少一个知识产权（IP），其中N是大于1的自然数。来自N个电力管理电路的第i（1

3. 发明授权

US08726047B2 System on chip, devices having the same, and method for power control of the SOC 有权
标题翻译：片上系统，具有相同功能的器件以及SOC功率控制方法
公开(公告)号：US08726047B2
公开(公告)日：2014-05-13
申请号：US13103535
申请日：2011-05-09
申请人： Jae Gon Lee , Jang Ho Cho , Bong Il Park , Kwang Ho Kim , Taek Kyun Shin , Dong Keun Kim , Jae Young Lee , Yung Hei Lee
发明人： Jae Gon Lee , Jang Ho Cho , Bong Il Park , Kwang Ho Kim , Taek Kyun Shin , Dong Keun Kim , Jae Young Lee , Yung Hei Lee
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.
摘要翻译：公开了一种包括多个功率域块的集成电路装置，其包括核心功率域块。功率控制电路被配置为独立地响应于来自核心功率域块的控制通信来控制提供给多个功率域块中的每一个的功率。功率控制电路分别包括与多个功率域块相对应的多个功率簇。多个功率群分别独立地响应于来自核心功率域块的控制通信来控制提供给多个功率域块的功率。

4. 发明授权

US09166567B2 Data-retained power-gating circuit and devices including the same 有权
标题翻译：数据保持功率门控电路和包括其的器件
公开(公告)号：US09166567B2
公开(公告)日：2015-10-20
申请号：US14210892
申请日：2014-03-14
申请人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
发明人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
IPC分类号： G05F1/10 , G05F3/02 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356008
摘要： A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.
摘要翻译：提供电源门控电路及包括其的装置。电源门控电路包括触发器，其被配置为接收第一电源电压和门控时钟信号以进行操作;以及开关电路，其连接在被配置为提供第一电源电压的第一电源电压源和第二电源电压电压源被配置为提供第二电源电压。开关电路包括第一开关，其被配置为连接在第一电源电压源和第二电源电压源之间并且响应于时钟使能信号而工作;第二开关被配置为连接在第一电源电压源和第二电源电压源，并响应于第一电源电压而工作。

5. 发明授权

US08969151B2 Integrated circuit system employing resistance altering techniques 有权
标题翻译：采用电阻改变技术的集成电路系统
公开(公告)号：US08969151B2
公开(公告)日：2015-03-03
申请号：US12040761
申请日：2008-02-29
申请人： Shyue Seng Tan , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee , Elgin Kiok Boone Quek
发明人： Shyue Seng Tan , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee , Elgin Kiok Boone Quek
IPC分类号： H01L21/8234 , H01L21/8244 , H01L27/06 , H01L21/8238 , H01L29/78 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/823807 , H01L29/7847
摘要： An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.
摘要翻译：一种集成电路系统，包括：提供包括第一区域和第二区域的衬底; 在第一区域上形成第一器件，在第二区域上形成电阻器件; 在所述衬底上形成第一电介质层和第二电介质层; 去除所述第二电介质层的一部分; 并退火集成电路系统以从电阻器件去除掺杂剂。

6. 发明授权

US08629503B2 Asymmetrical transistor device and method of fabrication 有权
标题翻译：非对称晶体管器件及其制造方法
公开(公告)号：US08629503B2
公开(公告)日：2014-01-14
申请号：US13366355
申请日：2012-02-06
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/66659 , H01L29/7848 , H01L29/78603 , H01L29/78618
摘要： Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.
摘要翻译：本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。掩埋绝缘介质层设置成与源区域的下表面邻接。

7. 发明授权

US08563386B2 Integrated circuit system with bandgap material and method of manufacture thereof 有权
标题翻译：具有带隙材料的集成电路系统及其制造方法
公开(公告)号：US08563386B2
公开(公告)日：2013-10-22
申请号：US12947530
申请日：2010-11-16
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
摘要翻译：一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

8. 发明申请

US20130138848A1 ASYNCHRONOUS BRIDGE 有权
标题翻译：异步桥
公开(公告)号：US20130138848A1
公开(公告)日：2013-05-30
申请号：US13617734
申请日：2012-09-14
申请人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
发明人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
IPC分类号： G06F13/38
CPC分类号： G06F13/405
摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.
摘要翻译：异步桥包括传输单元和接收单元。发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入数据，按读取地址指示。接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

9. 发明授权

US08338245B2 Integrated circuit system employing stress-engineered spacers 有权
标题翻译：采用应力工程间隔件的集成电路系统
公开(公告)号：US08338245B2
公开(公告)日：2012-12-25
申请号：US12048994
申请日：2008-03-14
申请人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
发明人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823864 , H01L27/0629 , H01L27/092 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.
摘要翻译：一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

10. 发明申请

US20120007180A1 FinFET with novel body contact for multiple Vt applications 有权
标题翻译： FinFET具有新的身体接触，适用于多种Vt应用
公开(公告)号：US20120007180A1
公开(公告)日：2012-01-12
申请号：US12803776
申请日：2010-07-06
申请人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
发明人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。因此，可以为不同的应用制造具有不同Vt的各种FinFET。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式